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nxp semiconductors data sheet: technical data document number: IMX6SLCEC rev. 5, 10/2017 package information plastic package 13 x 13 mm, 0.5 mm pitch ordering information see table 1 on page 3 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. mcimx6lxdvn10xx mcimx6lxevn10xx ordering information see table 1 on page 3 1 introduction the i.mx 6sololite processor represents the latest achievement in integrated multimedia applications processors, which are part of a growing family of multimedia-focused products that offer high performance processing and are optimized for lowest power consumption. the processor features nxp?s advanced implementation of the a single arm ? cortex ? -a9 mpcore? multicore processor, which operates at speeds up to 1 ghz. it includes 2d graphics processor and integrated power management. the proce ssor provides a 32-bit ddr3-800 memory interface and a number of other interfaces for connecting peripherals, such as wlan, bluetooth?, gps, hard drive, displays, and camera sensors. the i.mx 6sololite processor is specifically useful for applications, such as: ? color and monochrome ereaders ? entry level tablets ? barcode scanners i.mx 6sololite applications processors for consumer products 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 updated signal naming convention . . . . . . . . . . . . 7 2 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 special signal considerations. . . . . . . . . . . . . . . . 15 3.2 recommended connections for unused analog interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 17 4.2 power supplies requirements and restrictions . . 26 4.3 integrated ldo voltage regulator parameters . . . 27 4.4 plls electrical characteristics . . . . . . . . . . . . . . . 29 4.5 on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 30 4.6 i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . 31 4.7 i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . 35 4.8 output buffer impedance parameters . . . . . . . . . . 38 4.9 system modules timing . . . . . . . . . . . . . . . . . . . . 40 4.10 external peripheral interface parameters . . . . . . . 52 5 boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 80 5.1 boot mode configuration pins. . . . . . . . . . . . . . . . 80 5.2 boot devices interfaces allocation . . . . . . . . . . . . 81 6 package information and contact assignments . . . . . . . 82 6.1 updated signal naming convention . . . . . . . . . . . 82 6.2 13 x 13mm package information. . . . . . . . . . . . . . 83 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 2 nxp semiconductors introduction the i.mx 6sololite processor features: ? applications processor?the proces sor enhances the capabilities of high-tier portabl e applications by fulfilling the ever increasing mips requirements of operating sy stems and games. the dynamic voltage and frequency scaling (d vfs) provides significant powe r reduction, allowing the device to run at lower voltage and frequency with suff icient mips for tasks, such as audio decode. ? multilevel memory system?the multilevel memory system of each processor is based on the l1 instruction and data caches, l2 cache, and intern al and external memory. the processor supports many types of external memory devices, including ddr3, lpddr2, nor flash, psram, cellular ram, and managed nand, including emmc up to rev 4.4/4.41. ? smart speed technology?the processor has power management throughout the ic that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. smart speed technology enables the designe r to deliver a feature-rich product, requiring levels of power far lower than industry expectations. ? dynamic voltage and frequency sca ling?the processor im proves the power effi ciency of devices by scaling the voltage and fre quency to optimize performance. ? multimedia powerhouse?the multimedia performance of each processor is enhanced by a multilevel cache system, neon? mpe (media processor engine) co-processor, and a programmable smart dma (sdma) controller. ? powerful graphics acceleration?ea ch processor provides three in dependent, integrated graphics processing units: 2d blit engine, a 2d graphics accelerator, and dedicated openvg? 1.1 accelerator. ? interface flexibility?the processor supports connections to a vari ety of interfaces: lcd controller, cmos sensor interface (parallel), high-speed usb on-the-go with phy, high-speed usb host phy, multiple expansion card ports (high-speed mmc/sdio host and other), 10/100 mbps ethernet controller, and a variety of other popular interfaces (such as uart, i 2 c, and i 2 s serial audio). ? electronic paper display controll er?the processor integrates epd controller that supports e ink color and monochrome with up to 2048 x 1536 resolution at 106 hz refresh, 4096 x 4096 resolution at 20 hz refresh and 5-bit grayscal e (32-levels per color channel). ? advanced security?the processor de livers hardware-enabled security features that enable secure e-commerce, digital rights manage ment (drm), information encryption, secure boot, and secure software downloads. the security f eatures are discussed in detail in the i.mx 6sololite security reference manual (imx6slsrm). contact your local nxp representative for more information. ? integrated power management?the processor integrates linear regul ators and generate internally all the voltage levels for di fferent domains. this signifi cantly simplifies system power management structure. ? gpio with interrupt capabiliti es?the new gpio pad design suppor ts configurable dual voltage rails at 1.8 v and 3.3 v supplies. the pad is confi gurable to interface at either voltage level. 1.1 ordering information table 1 provides examples of or derable part numbers cove red by this data sheet. table 1 does not include all possible orderable part numbers. the latest part numbers are available on nxp.com/imx6series . if your
introduction i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 3 desired part number is not listed in table 1 , or you have questions a bout available parts, see nxp.com/imx6series or contact your nxp representative. figure 1 describes the part number nomencl ature so that users can identify the characteristics of the specific part number they ha ve (for example, cores, frequency, temperature grad e, fuse options, silicon revision). table 1. example orderable part numbers part number options speed grade 1 1 if a 24 mhz input clock is used (required for u sb), the maximum soc speed is limited to 996 mhz. temperature (tj) package 2 2 case 2240 is rohs compliant, lead-fre e moisture sensitivity level 3 (msl). mcimx6l8dvn10ab gpu, epdc 1ghz 0 c to +95 c 13x13mm, 0.5mm pitch bga mcimx6l8dvn10ac gpu, epdc 1ghz 0 c to +95 c 13x13mm, 0.5mm pitch bga mcimx6l7dvn10ab epdc, no gpu 1ghz 0 c to +95 c 13x13mm, 0.5mm pitch bga mcimx6l7dvn10ac epdc, no gpu 1ghz 0 c to +95 c 13x13mm, 0.5mm pitch bga mcimx6l3dvn10ab gpu, no epdc 1ghz 0 c to +95 c 13x13mm, 0.5mm pitch bga mcimx6l3dvn10ac gpu, no epdc 1ghz 0 c to +95 c 13x13mm, 0.5mm pitch bga mcimx6l3evn10ab gpu, no epdc 1ghz -40 c to +105 c 13x13mm, 0.5mm pitch bga mcimx6l3evn10ac gpu, no epdc 1ghz -40 c to +105 c 13x13mm, 0.5mm pitch bga mcimx6l2dvn10ab no gpu, no epdc 1ghz 0 c to +95 c 13x13mm, 0.5mm pitch bga mcimx6l2dvn10ac no gpu, no epdc 1ghz 0 c to +95 c 13x13mm, 0.5mm pitch bga mcimx6l2evn10ab no gpu, no epdc 1ghz -40 c to +105 c 13x13mm, 0.5mm pitch bga mcimx6l2evn10ac no gpu, no epdc 1ghz -40 c to +105 c 13x13mm, 0.5mm pitch bga
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 4 nxp semiconductors introduction figure 1. part number nomenclature?i.mx 6sololite 1.2 features the i.mx 6sololite processor is based on arm cort ex-a9 mpcore multicore processor, which has the following features: ? arm cortex-a9 mpcore cpu processor (with trustzone) ? the core configuration is symmetric, where each core includes: ? 32 kbyte l1 instruction cache ? 32 kbyte l1 data cache ? private timer and watchdog ? cortex-a9 neon mpe (media processing engine) co-processor the arm cortex-a9 mpcore complex includes: ? general interrupt controller (gic) with 128 interrupt support ? global timer ? snoop control unit (scu) ? 256 kb unified i/d l2 cache ? two master axi (64-bit) bus interfaces output of l2 cache ? frequency of the core (includi ng neon and l1 cache) as per table 9, "operating ranges," on page 21 qualification level mc prototype samples pc mass production mc special sc part # series x i.mx 6sololite l silicon revision 1 a rev 1.0 a rev 1.2 rev 1.3 b 2 rev 1.4 c mc imx6 x @ + vv $$ % a part differentiator @ gpu, epd 8 no gpu, epd 7 gpu, no epd 3 no gpu, no epd 2 fusing % supports e-ink epdc if epd enabled a frequency $$ 1 ghz 10 package type rohs mapbga 13x13 0.5mm vn temperature tj + commercial: 0 to + 95 cd extended commercial: -40 to + 105 ce 1. see the nxp.com\imx6series web page for latest information on the available silicon revision. 2. rev 1.2 (usb_analog_digprog register = 0x0062_0002) rev 1.3 (usb_analog_digprog register = 0x0062_0003)
introduction i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 5 ? neon mpe coprocessor ? simd media processing architecture ? neon register file with 32x64-bit general-purpose registers ? neon integer execute pipeline (alu, shift, mac) ? neon dual, single-precision floating poi nt execute pipeline (fadd, fmul) ? neon load/store and permute pipeline the soc-level memory system consists of the following a dditional components: ? boot rom, including hab (96 kb) ? internal multimedia / shared, fast access ram (ocram, 128 kb) ? external memory interfaces: ? 16-bit, and 32-bit ddr3 -800, and lpddr2-800 channels ? 16/32-bit nor flash. ? 16/32-bit psram, cellular ram (32 bits or less) each i.mx 6sololite processor enables the following interfaces to exte rnal devices (some of them are muxed and not available simultaneously): ? displays?total of three interfaces are available. ? lcd, 24-bit display port, up to 225 mpix els/sec (for example, wuxga at 60 hz) ? epdc, color, and monochrome e ink, up to 1650 x 2332 resolution and 5-bit grayscale ? camera sensors: ? parallel camera port (up to 16-bit and up to 66 mhz peak) ? expansion cards: ? four mmc/sd/sdio card ports all supporting: ? 1-bit or 4-bit transfer mode specifications for sd and sdio cards up to uhs-i sdr-104 mode (104 mb/s max) ? 1-bit, 4-bit, or 8-bit transfer mode specific ations for mmc cards up to 52 mhz in both sdr and ddr modes (104 mb/s max) ? 4-bit or 8-bit transfer m ode specifications for emmc ch ips up to 200 mhz in hs200 mode (200 mb/s max) ?usb : ? two high speed (hs) usb 2.0 otg (up to 480 mbps), with integrated hs usb phy ? one usb 2.0 (480 mbps) hosts: ? one hs hosts with integrated hs-ic usb (high speed inter-chip usb) phy ? miscellaneous ips and interfaces: ? ssi block?capable of supporting audio sample frequencies up to 192 khz stereo inputs and outputs with i 2 s mode ? five uarts, up to 5.0 mbps each: ? providing rs232 interface ? supporting 9-bit rs485 multidrop mode
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 6 nxp semiconductors introduction ? one of the five uarts (uart1) supports 8-wire while others four s upports 4-wire. this is due to the soc iomux limitation, since all uart ips are identical. ? four ecspi (enhanced cspi) ? three i 2 c, supporting 400 kbps ? ethernet controller, 10/100 mbps ? four pulse width modulators (pwm) ? system jtag controller (sjc) ? gpio with interrupt capabilities ? 8x8 key pad port (kpp) ? sony philips digital interface (spdif), rx and tx ? two watchdog timers (wdog) ? audio mux (audmux) the i.mx 6sololite processor integrates adva nced power management unit and controllers: ? provide pmu, including ldo su pplies, for on-chip resources ? use temperature sensor for monitoring the die temperature ? support dvfs techniques for low power modes ? use software state retention and power gating for arm and mpe ? support various levels of system power modes ? use flexible clock gating control scheme the i.mx 6sololite processor uses dedicated hardwa re accelerators to meet th e targeted multimedia performance. the use of hardware a ccelerators is a key factor in obtai ning high performance at low power consumption numbers, while having the cpu core relatively free for performing other tasks. the i.mx 6sololite processor incorporat es the following hardware accelerators: ? gpu2dv2?2d graphics pro cessing unit (bitblt). ? gpuvg?openvg 1.1 graphics processing unit. ? pxp?pixel processing pipeline. off loading ke y pixel processing operations are required to support the epd disp lay applications. security functions are enabled and accelerated by the following hardware: ? arm trustzone including the tz architecture (sep aration of interrupts, memory mapping, and so on.) ? sjc?system jtag controller. protecting jt ag from debug port attacks by regulating or blocking the access to th e system debug features. ? snvs?secure non-volatile storage, including secure real time clock. ? csu?central security unit. enhancement for the ic identification module (iim). will be configured during boot and by efus es and will determine the secu rity level operation mode as well as the tz policy. ? a-hab?advanced high assurance boot?hab v4 with the new embedded enhancements: sha-256, 2048-bit rsa key, versi on control mechanism, warm boot , csu, and tz initialization.
introduction i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 7 note the actual feature set depends on th e part numbers as described in table 1, "example orderable part numbers," on page 3 . functions, such as 2d hardware graphics accelerat ion or e ink may not be enabled for specific part numbers. 1.3 updated signal naming convention the signal names of the i.mx6 series of products have been standardized to bett er align the signal names within the family and across the documentation. some of the benefits of thes e changes are as follows: ? the names are unique within the scope of an soc and within the series of products ? searches will return all occurrences of the named signal ? the names are consistent be tween i.mx 6 series products implementing the same modules ? the module instance is incorporated into the signal name this change applies only to signal na mes. the original ball names have been preserved to prevent the need to change schematics, bsdl m odels, ibis models, and so on. throughout this document, the updated signal names are used except where referenced as a ball name (such as the functional contact assignm ents table, ball map table, and so on). a master list of the signal name changes is in the document, imx 6 series signal name mapping (eb792). this list can be used to map the signal names used in older documentati on to the new standardized naming conventions.
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 8 nxp semiconductors architectural overview 2 architectural overview the following subsections provide an architectural overview of the i.mx 6sololite processor system. 2.1 block diagram figure 2 shows the functional modules in th e i.mx 6sololite processor system. figure 2. i.mx 6sololite system block diagram note the numbers in brackets indicate numbe r of module instances. for example, pwm (4) indicates four separate pwm peripherals.
modules list i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 9 3 modules list the i.mx 6sololite processor contains a variety of digital and analog modules. table 2 describes these modules in alphabetical order. table 2. i.mx 6sololite modules list block mnemonic block name subsystem brief description 128x8 fuse box electrical fuse array security electrical fuse array. enables to se tup boot modes, security levels, security keys, and many other system parameters. the i.mx 6sololite processor consists of 2-128x8-bit fuse box accessible through ocotp_ctrl interface. arm arm platform arm the arm cortex-a9 platform consists of a cortex-a9 core version r2p10 and associated sub-blocks, including level 2 cache controller, scu (snoop control unit), gic (general interrupt controller), private timers, watchdog, and coresight debug modules. audmux digital audio mux multimedia peripherals the audmux is a programmable interconnect for voice, audio, and synchronous data routing between host seri al interfaces (for example, ssi1, ssi2, and ssi3) and peripheral serial interfaces (audio and voice codecs). the audmux has seven ports with identical functionality and programming models. a desired connectivity is achieved by configuring two or more audmux ports. ccm gpc src clock control module, general power controller, system reset controller clocks, resets, and power control these modules are responsible for clock and reset distribution in the system, and also for the system power management. csu central security unit security the central security unit (csu) is responsible for setting comprehensive security policy within the i.mx 6sololite platform. the security control registers (scr) of the csu are set du ring boot time by the hab and are locked to prevent further writing. cti-1 cti-2 cti-3 cti-4 cti-5 cross trigger interfaces debug / trace cross trigger interfaces allows cr oss-triggering based on inputs from masters attached to ctis. the cti module is internal to the cortex-a9 core platform. ctm cross trigger matrix debug / trace cross trigger matrix ip is us ed to route triggering events between ctis. the ctm module is internal to the cortex-a9 core platform. dap debug access port system control peripherals the dap provides real-time access for the debugger without halting the core to: ? system memory and peripheral registers ? all debug configuration registers the dap also provides debugger access to jtag scan chains. the dap module is internal to the cortex-a9 core platform. dcp data co-processor security this module provides support for general encryption and hashing functions typically used for security functions. because its basic job is moving data from memory to memory, it also incorporates a memory-copy (memcopy) function for both debugging and as a more efficient method of copying data between memory blocks than the dma-based approach.
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 10 nxp semiconductors modules list ecspi-1 ecspi-2 ecspi-3 ecspi-4 configurable spi connectivity peripherals full-duplex enhanced synchronous serial interface. it is configurable to support master/slave modes, four chip selects to support multiple peripherals. eim nor-flash /psram interface connectivity peripherals the eim nor-flash / psram provides: ? support 16-bit (in muxed io mode only) psram memories (sync and async operating modes), at slow frequency ? support 16-bit (in muxed io mode only) nor-flash memories, at slow frequency ? multiple chip selects epdc electrophoretic display controller peripherals the epdc is a feature-rich, low power, and high-performance direct-drive, active matrix epd controller. it is specifically designed to drive e ink epd panels, supporting a wide variety of tft backplanes. epit-1 epit-2 enhanced periodic interrupt timer timer peripherals each epit is a 32-bit set and forget timer that starts co unting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. it has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter value can be programmed on the fly. fec fast ethernet controller connectivity peripherals the ethernet media access controller (mac) is designed to support 10 and 100 mbps ethernet/ieee 802.3 networks. an external transceiver interface and transceiver function are required to complete the interface to the media. gpio-1 gpio-2 gpio-3 gpio-4 gpio-5 general purpose i/o modules system control peripherals used for general purpose input/output to external ics. each gpio module supports 32 bits of i/o. gpt general purpose timer timer peripherals each gpt is a 32-bit free-running or set and forget mode timer with programmable prescaler and compare and capture register. a timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. when the timer is configured to operate in s et and forget mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. the counter has output compare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. gpu2dv2 graphics processing unit-2d, ver 2 multimedia peripherals the gpu2dv2 provides hardware acceleration for 2d graphics algorithms, such as bit blt, stretch blt, and many other 2d functions. gpuvgv2 vector graphics processing unit, ver2 multimedia peripherals openvg graphics accelerator provides openvg 1.1 support as well as other accelerations, including real-time hardware curve tesselation of lines, quadratic and cubic bezier curves, 16x line anti-aliasing, and various vector drawing functions. i 2 c-1 i 2 c-2 i 2 c-3 i 2 c interface connectivity peripherals i 2 c provide serial interface for external devices. data rates of up to 400 kbps are supported. table 2. i.mx 6sololite modules list (continued) block mnemonic block name subsystem brief description
modules list i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 11 iomuxc iomux control system control peripherals this module enables flexible io multiplexing. each io pad has default and several alternate functions. the alternat e functions are software configurable. kpp key pad port connectivity peripherals kpp supports 8 x 8 external ke y pad matrix. kpp features are: ? open drain design ? glitch suppression circuit design ? multiple keys detection ? standby key press detection lcdif lcd interface multimedia peripherals the lcdif provides display data for external lcd panels from simple text-only displays to wvga, 16/18/24 bpp color tft panels. the lcdif supports all of these different interfaces by providing fully programmable functionality and sharing register space, fifos, and alu resources at the same time. the lcdif supports rgb (dotclk) modes as well as system mode including both vsync and wsync modes. mmdc ddr controller connectivity peripherals ddr controller has the following features: ? support 16/32-bit ddr3-800 or lpddr2-800 ? supports up to 2 gbyte ddr memory space ocotp_ ctrl otp controller security the on-chip otp controller (ocotp_ctrl) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. the module supports electrically-programmable poly fuses (efuses). the ocotp_ctrl also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non-volatility. the ocotp_ctrl provides the primary user-visible mechanism for interfacing with on-chip fuse elements. among the uses for the fuses are unique chip identifiers, mask revision numbers, cr yptographic keys, jtag secure mode, boot characteristics, and various control signals, requiring permanent non-volatility. ocram on-chip memory controller data path the on-chip memory controller (o cram) module is designed as an interface between systems axi bus and internal (on-chip) sram memory module. in i.mx 6sololite processor, the oc ram is used for controlling the 128 kb multimedia ram through a 64-bit axi bus. ocram_l2 on-chip memory controller for l2 cache data path the on-chip memory controller for l2 cache (ocram_l2) module is designed as an interface between systems axi bus and internal (on-chip) l2 cache memory module during boot mode. osc 32 khz osc 32 khz clocking generates 32.768 khz clock from external crystal. pmu power management functions data path integrated power management unit. used to provide power to various soc domains. pwm-1 pwm-2 pwm-3 pwm-4 pulse width modulation connectivity peripherals the pulse-width modulator (pwm) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. it uses 16-bit resolution and a 4x16 data fifo to generate sound. table 2. i.mx 6sololite modules list (continued) block mnemonic block name subsystem brief description
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 12 nxp semiconductors modules list pxp pixel processing pipeline display peripherals a high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, gamma-mapping, and rotation. the pxp is enhanced with features specifically for gray scale applications. in addition, the pxp supports traditional pixel/frame processing paths for still- image and video processing applications, allowing it to interface with either of the integrated epd controllers. ram 128 kb internal ram internal memory internal ram, which is accessed through ocram memory controller. rngb random number generator security random number generating module. rom 96kb boot rom internal memory supports secure and regular boot modes. includes read protection on 4k region for content protection. romcp rom controller with patch data path rom controller with rom patch support. sdma smart direct memory access system control peripherals the sdma is multi-channel flexible dma engine. it helps in maximizing system performance by off-loading the various cores in dynamic data routing. it has the following features: ? powered by a 16-bit inst ruction-set micro-risc engine ? multi-channel dma supporting up to 32 time-division multiplexed dma channels ? 48 events with total flexibility to trigger any combination of channels ? memory accesses including linear, fifo, and 2d addressing ? shared peripherals between arm and sdma ? very fast context-software switching with 2-level priority based preemptive multi-tasking ? dma units with auto-flush and prefetch capability ? flexible address management for dma transfers (increment, decrement, and no address changes on source and destination address) ? dma ports can handle unit-directional and bi-directional flows (copy mode) ? up to 8-word buffer for configurable burst transfers ? support of byte-swapping and crc calculations ? library of scripts and api is available sjc system jtag controller system control peripherals the sjc provides jtag interface, which complies with jtag tap standards, to internal logic. the i.mx 6sololite processor uses jtag port for production, testing, and system debugging. in addi tion, the sjc provides bsr (boundary scan register) standard support, which complies with ieee1149.1 and ieee1149.6 standards. the jtag port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. the i.mx 6sol olite sjc incorporates three security modes for protecting against unauthorized accesses. modes are selected through efuse configuration. snvs secure non-volatile storage security secure non-volatile storage, incl uding secure real time clock, security state machine, master key control, and violation/tamper detection and reporting. spdif sony phillips digital interface multimedia peripherals a standard audio file transfer format, developed jointly by the sony and phillips corporations. has transmitter and receiver functionality. table 2. i.mx 6sololite modules list (continued) block mnemonic block name subsystem brief description
modules list i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 13 ssi-1 ssi-2 ssi-3 i2s/ssi/ac97 interface connectivity peripherals the ssi is a full-duplex synchronous interface, which is used on the ap to provide connectivity with off-chip audio peripherals. the ssi supports a wide variety of protocols (ssi normal, ssi network, i2s, and ac-97), bit depths (up to 24 bits per word), and clock / frame sync options. the ssi has two pairs of 8x24 fifos and hardware support for an external dma controller in order to minimize its impact on system performance. the second pair of fifos provides hardware interleaving of a second audio stream that reduces cpu overhead in use cases where two time slots are being used simultaneously. tempmon temperature monitor system control peripherals the temperature monitor/sensor ip, fo r detecting high temperature conditions. the temperature sensor ip for detect ing die temperature. the temperature read out does not reflect case or ambien t temperature, but the proximity of the temperature sensor location on the die. temperature distribution may not be uniformly distributed, therefore the read out value may not be the reflection of the temperature value of the entire die. tzasc trust-zone address space controller security the tzasc (tzc-380 by arm) provides security address region control functions required for intended application. it is used on the path to the dram controller. uart-1 uart-2 uart-3 uart-4 uart-5 uart interface connectivity peripherals each of the uartv2 modules support the following serial data transmit/receive protocols and configurations: ? 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none) ? programmable baud rates up to 5.0 mbps. ? 32-byte fifo on tx and 32 half-word fifo on rx supporting auto-baud ? irda 1.0 support (up to sir speed of 115200 bps) ? option to operate as 8-pins full uart, dce, or dte usboh2a 2x usb 2.0 high speed otg and 1x hs hosts connectivity peripherals usbo2h contains: ? two high-speed otg module with integrated hs usb phy ? one identical high-speed host modules connected to hsic usb ports table 2. i.mx 6sololite modules list (continued) block mnemonic block name subsystem brief description
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 14 nxp semiconductors modules list usdhc-1 usdhc-2 usdhc-2 usdhc-4 sd/mmc and sdxc enhanced multi-media card / secure digital host controller connectivity peripherals i.mx 6sololite specific soc characteristics: all four mmc/sd/sdio controller ips are identical and are based on the usdhc ip. they are: ? conforms to the sd host controll er standard specification version 3.0. ? fully compliant with mmc command/response sets and physical layer as defined in the multimedia card system specification, v4.2/4.3/4.4/4.41/4.5 including high-capacity (size > 2 gb ) cards hc mmc. hardware reset as specified for emmc cards is supported at ports 3 and 4 only. ? fully compliant with sd command/response sets and physical layer as defined in the sd memory card specif ications, v3.0 including high-capacity sdhc cards up to 32 gb and sdxc cards up to 2 tb. ? fully compliant with sdio command/response sets and interrupt/read-wait mode as defined in the sdio card specification, part e1, v1.10 ? fully compliant with sd card specif ication, part a2, sd host controller standard specification, v2.00 all four ports support: ? 1-bit or 4-bit transfer mode specif ications for sd and sdio cards up to uhs-i sdr104 mode (104 mb/s max) ? 1-bit, 4-bit, or 8-bit transfer mode specifications for mmc cards up to 52 mhz in both sdr and ddr modes (104 mb/s max) ? 4-bit or 8-bit transfer mode specificat ions for emmc chips up to 200 mhz in hs200 mode (200 mb/s max) however, the soc level integration and i/o muxing logic restrict the functionality to the following: ? instances 1 and 2 are primarily intended to serve as external slots or interfaces to on-board sdio devices. these ports are equipped with card detection and write protection pad s and do not support hardware reset. ? all ports can work with 1.8 v and 3.3 v cards. there are two completely independent i/o power domains for ports 1 and 2 in four bit configuration (sd interface). port 3 is placed in an independent power domain and port 4 shares its power domain with other interfaces. wdog-1 watchdog timer peripherals the watchdog timer supports two comparison points during each counting period. each of the comparison points is configurable to evoke an interrupt to the arm core, and a second point evokes an external event on the wdog line. wdog-2 (tz) watchdog (trustzone) timer peripherals the trustzone watchdog (tz wdog) timer module protects against trustzone starvation by providing a method of escaping normal mode and forcing a switch to the tz mode. tz st arvation is a situation where the normal os prevents switching to the tz mode. su ch situation is undesirable as it can compromise the systems security. once the tz wdog module is activated, it must be serviced by tz software on a periodic basis. if servicing does not take place, the timer times out. upon a ti me-out, the tz wdog asserts a tz mapped interrupt that forces switching to the tz mode. if it is still not served, the tz wdog asserts a security violation signal to the csu. the tz wdog module cannot be programmed or deactivated by a normal mode software. xtalosc crystal oscillator i/f clocking the xtalosc module enables connectivity to external crystal oscillator device. in a typical application use-case, it is used for 24 mhz oscillator. table 2. i.mx 6sololite modules list (continued) block mnemonic block name subsystem brief description
modules list i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 15 3.1 special signal considerations table 3 lists special signal considerations for the i.mx 6s ololite processor. the si gnal names are listed in alphabetical order. the package contact assign ments can be found in section 6, ?package information and contact assignments.? signal descriptions are provided in the i.mx 6sololite reference manual (imx6slrm). table 3. special signal considerations signal name remarks xtalosc_clk1_p/ xtalosc_clk1_n one general purpose differential high speed clock input/output is provided. it could be used to: ? to feed external reference clock to the plls and further to the modules inside soc, for example as alternate reference clock for audio interfaces, etc. ? to output internal soc clock to be used outside th e soc as either reference clock or as a functional clock for peripherals. see the i.mx 6sololite reference manual for details on the respective clock trees. the clock inputs/outputs are lvds differential pairs compatible with tia/eia- 644 standard, the maximum clock out frequency range supported is 528 mhz. alternatively one may use single ended signal to dr ive xtalosc_clk1_p input. in this case, the corresponding xtalosc_clk1_n input should be tied to the constant voltage level equal 1/2 of the input signal swing. termination should be provided in case of high frequency signals. see lvds pad electrical specification for further details. after initialization, the xtalosc_clk1 input/output could be disabled (if not used). if unused, the xtalosc_clk1_n/p pair can remain unconnected. dram_vref when using dram_vref with ddr i/o, the nominal reference voltage must be half of the nvcc_dram supply. the user must tie dram_vref to a precision external resistor divider. use a 1 k 0.5% resistor to gnd and a 1 k 0.5% resistor to nvcc_dram. shunt eac h resistor with a closely-mounted 0.1 f capacitor. to reduce supply current, a pair of 1.5 k 0.1% resistors can be used. using resistors with recommended tolerances ensures the 2% dram_vref tolerance ( per the ddr3 specification) is maintained when four ddr3 ics plus the i.mx 6sololite ar e drawing current on the resistor divider. it is recommended to use regulated power supply for big memory configurations (more that eight devices). jtag_ nnnn the jtag interface is summarized in ta bl e 4 . use of external resistors is unnecessary. however, if external resistors are used, the user must ensure th at the on-chip pull-up/down configuration is followed. for example, do not use an external pull down on an input that has on-chip pull-up. jtag_tdo is configured with a keeper circuit such that the floating cond ition is eliminated if an external pull resistor is not present. an external pull resist or on jtag_tdo is detrimental and should be avoided. jtag_mode must be externally connected to gnd fo r normal operation. termination to gnd through an external pull-down resistor (such as 1 k ) is allowed. jtag_mode set to high configures the jtag interface to mode compliant with ieee1149.1 standar d. jtag_mode set to low configures the jtag interface for common software debug adding all the system taps to the chain. nc these signals are no connect (nc) and must remain unconnected by the user. src_onoff in normal mode may be connected to onoff button (de-bouncing provided at this input). internally this pad is pulled up. a short duration (<5s) connection to gnd in off mode causes the internal power management state machine to change the state to on. in on mode, a short duration connection to gnd generates interrupt (intended to initiate a software co ntrollable power down). a long duration (above ~5s) connection to gnd causes forced off. src_por_b this cold reset negative logic input resets all modules and logic in the ic.
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 16 nxp semiconductors modules list rtc_xtali/ rtc_xtalo if the user wishes to configure rtc_xtali and rtc_xtalo as an rtc oscillator, a 32.768 khz crystal ( 100 k esr, 10 pf load) should be connected between rtc_xtali and rtc_xtalo. keep in mind the capacitors implemented on either side of the cryst al are about twice the crystal load capacitor. to hit the exact oscillation frequency, the board capacitors need to be reduced to account for board and chip parasitics. the integrated oscillation amplifier is self biasing, but relatively weak. care must be taken to limit parasitic leakage from rtc_xtali and rtc_xtalo to either power or ground (>100 m ). this will debias the amplifier and cause a reduction of startup margin. typically rtc_xtali and rtc_xtalo should bias to approximately 0.5 v. if it is desired to feed an external low frequency clock into rtc_xtali, the rtc_xtalo pin must remain unconnected or driven with a complimentary signal. th e logic level of this forcing clock should not exceed vdd_snvs_cap level and the frequency should be <100 khz under typical conditions. in the case when a high accuracy real time clock is not required, the system may use an internal low frequency ring oscillator. it is recommended to connect rtc_xtali to gnd and leave rtc_xtalo unconnected. test_mode test_mode is for nxp factory use. this signal is internally connected to an on-chip pull-down device. the user must either leave this signal unconnected or tie it to gnd. xtali/xtalo ? a 24.0 mhz crystal must be connected between xtali and xtalo. the level and frequency must be <32 mhz under typical conditions. ? the crystal must be rated for a maximum drive level of 250 w. an esr (equivalent series resistance) of typically 80 is recommended. nxp bsp (board support package) software requires 24 mhz on xtali/xtalo. ? the crystal can be eliminated if an external 24 mhz oscillator is available in the system. in this case, xtali must be directly driven by the external oscillator and xtalo remains unconnected. the xtali signal level must swing from ~0.8 x nvcc_pll_out to ~0.2 v. ? this clock is used as a reference for usb, so there are strict frequen cy tolerance and jitter requirements. ? see the xtalosc chapter and relevant interface specifications chapters of the i.mx 6sololite reference manual (imx6slrm), for details. zqpad dram calibration resistor 240 1 % used as reference during dram output buffer driver calibration should be connected between this pad and gnd. table 4. jtag controller interface summary jtag i/o type on-chip termination jtag_tck input 47 k pull-up jtag_tms input 47 k pull-up jtag_tdi input 47 k pull-up jtag_tdo 3-state output keeper jtag_trst_b input 47 k pull-up jtag_mode input 100 k pull-up table 3. special signal considerations (continued) signal name remarks
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 17 3.2 recommended connections for unused analog interfaces table 5 shows the recommended connecti ons for unused analog interfaces. 4 electrical characteristics this section provides the device and module-level electrical characteristics for the i.mx 6sololite. 4.1 chip-level conditions this section provides the device-level el ectrical characteristics for the ic. see table 6 for a quick reference to the individual tables and sections. 4.1.1 absolute maximum ratings caution stresses beyond those listed under table 7 may cause permanent damage to the device. these are stress ratings onl y. functional operation of the device at these or any other conditions beyond those indicated in the table 9, "operating ranges ? or subsequent parameters tables is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. table 7 provides the absolute maximum operating ratings. table 5. recommended connections for unused analog interfaces module pad name recommendations if unused? xtalosc xtalosc_clk1_n, xtalosc_clk1_p leave unconnected usb usb_otgx_dn, usb_otgx_dp, usb_otgx_vbus, usb_otg_chd_b leave unconnected table 6. i.mx 6sololite chip-level conditions for these characteristics, ? topic appears ? absolute maximum ratings on page 18 bga case 2240 package thermal resistance on page 19 operating ranges on page 21 external clock sources on page 23 maximum supply currents on page 24 low power mode supply currents on page 25 usb phy current consumption on page 26
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 18 nxp semiconductors electrical characteristics 4.1.2 thermal resistance note per jedec jesd51-2, the intent of th ermal resistance measurements is solely for a thermal performance compar ison of one package to another in a standardized environment. this met hodology is not meant to and will not predict the performance of a pack age in an application-specific environment. table 7. absolute maximum ratings parameter description symbol min max unit core supply input voltage (ldo enabled) vdd_arm_in vdd_soc_in vdd_pu_in -0.3 1.6 v core supply input voltage (ldo bypass) vdd_arm_in vdd_soc_in vdd_pu_in -0.3 1.4 v core supply output voltage (ldo enabled) vdd_arm_cap vdd_soc_cap vdd_pu_cap -0.3 1.4 v vdd_high_in supply voltage vdd_high_in -0.3 3.7 v vdd_high_cap supply output voltage vdd_high_cap -0.3 2.6 v ddr i/o supply voltage nvcc_dram -0.4 1.975 (see note 1) 1 the absolute maximum voltage includes an allowance for 400 mv of overshoot on the io pins. per jedec standards, the allowed signal overshoot must be derated if nvcc_dram exceeds 1.575v. v ddr pre-drivers supply voltage nvcc_dram_2p5 -0.3 2.85 v gpio dual supply 1p8v i/o supply voltage nvcc18_io -0.5 2.1 v gpio dual supply 3p3v i/o supply voltage nvcc33_io -0.5 3.7 v snvs in supply voltage (secure non-volatile storage and real time clock) vdd_snvs_in -0.3 3.7 v usb i/o supply voltage usb_h1_dn usb_h1_dp usb_otg_dn usb_otg_dp usb_otg_chd_b -0.3 3.63 v usb vbus supply voltage usb_otg_vbus 5.25 v v in /v out i/o voltage range (non-ddr pins) v in /v out -0.5 ovdd+0.3 (see note 2) 2 ovdd is the i/o supply voltage. v v in /v out i/o voltage range (ddr pins) v in /v out -0.5 ovdd+0.4 (see notes1& 2) v esd immunity (hbm) vesd_hbm 2000 v esd immunity (cdm) vesd_cdm 500 v storage temperature range t storage -40 150 o c
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 19 4.1.2.1 bga case 2240 package thermal resistance table 8 provides the mapbga packag e thermal resistance data. 4.1.3 operating ranges figure 3 shows major power systems blocks and internal /external connections fo r the i.mx 6sololite processor. table 8. package thermal resistance data rating board symbol no lid unit junction to ambient 1 (natural convection) 1 junction-to-ambient thermal resistance was determined pe r jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board (1s) r ja 51 c/w four layer board (2s2p) r ja 28 c/w junction to ambient 1 (at 200 ft/min) single layer board (1s) r jma 40 c/w four layer board (2s2p) r jma 24 c/w junction to board 2 2 junction-to-board thermal resistance was determined per jede c jesd51-8. thermal test board meets jedec specification for the specified package. r jb 14 c/w junction to case 3 (top) 3 junction-to-case at the top of the package was determined by using mil-std 883 method 1012.1 . the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. r jctop 9c/w junction to package top 4 4 thermal characterization parameter indica ting the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters ar e not available, the thermal characteriza tion parameter is written as psi-jt. natural convection jt 2c/w
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 20 nxp semiconductors electrical characteristics figure 3. i.mx 6sololite soc power block diagram exter nal suppl i es dcdc low ldo_pu gpu2d openvg ldo_arm l1 cache arm cor e ldo_soc soc ldo_2p5 efuse usb plls lvds ldo_1p1 24m osc ldo_snvs snvs 32k osc ldo_usb dcdc high coi n cel l usb_otg2_vbus vddpu_cap i.mx 6sl chip vddpu_in vddarm_in gnd gnd gnd gnd gnd gnd gnd vddarm_cap vddsoc_cap vddhigh_cap nvcc_pll_ou t vddsnvs_cap vddusb_cap vddsnvs_i n vddhigh_in vddsoc_i n usb_otg1_vbus l2 cache sw itch di s pl ay sw itch
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 21 table 9 provides the operating ranges of the i.mx 6solol ite processor. for details on the chip's power structure, see the ?power manageme nt unit (pmu)? chapter of the i.mx 6sololite reference manual ( imx6slrm ) . table 9. operating ranges parameter description symbol min typ max 1 unit comment run mode: ldo enabled vdd_arm_in 1.375 2 1.5 v ldo output set at 1.250v minimum for operation up to 996 mhz 1.275 2 1.5 v ldo output set at 1.150v minimum for operation up to 792 mhz 1.075 2 1.5 v ldo output set at 0.95v minimum for operation up to 396 mhz 1.075 2 1.5 v ldo output set at 0.950v minimum for operation up to 192 mhz 1.050 2 1.5 v ldo output set at 0.9250v minimum for operation up to 24 mhz vdd_soc_in 3 vdd_pu_in 1.275 2,4 1.5 v vdd_soc and vdd_pu ldo outputs (vdd_soc_cap and vdd_pu_cap) require 1.15 v minimum run mode: ldo bypassed vdd_arm_in 1.250 1.3 v ldo bypassed for operation up to 996 mhz 1.150 1.3 v ldo bypassed for operation up to 792 mhz 0.950 1.3 v ldo bypassed for operation up to 396 mhz 0.950 1.3 v ldo bypassed for operation up to 192 mhz 0.925 1.3 v ldo bypassed for operation up to 24 mhz vdd_soc_in 3 vdd_pu_in 1.15 4 1.3v standby/dsm mode vdd_arm_in 0.9 1.3 v see table 12, "stop mode current and power consumption," on page 25 . vdd_soc_in vdd_pu_in 0.9 1.3 v vddhigh internal regulator vdd_high_in 5 2.8 3.3 v must match the ra nge of voltages that the rechargeable backup battery supports. backup battery supply range vdd_snvs_in 5 2.7 3.6 v should be supplied from the same supply as vdd_high_in if th e system does not require keeping real time and other data on off state. usb supply voltages usb_otg1_vbus usb_otg2_vbus 4.4 5.25 v ddr i/o supply nvcc_dram 1.14 1.2 1.3 v lpddr2 1.425 1.5 1.575 v ddr3 nvcc_dram_2p5 2.5 2.5 2.75 v
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 22 nxp semiconductors electrical characteristics 4.1.4 external clock sources each i.mx 6sololite processor has two external input system clocks : a low frequency (rtc_xtali) and a high frequency (xtali). the rtc_xtali is used for low-frequency functio ns. it supplies the clock for wake-up circuit, power-down real time clock operation, and slow syst em and watchdog counters. the clock input can be connected to either an external osci llator or a crystal using the internal oscillator amplif ier. additionally, there is an internal ring oscillator, which can substitute the rtc_xtali, in case accuracy is not important. the system clock input xtali is used to generate the main system cl ock. it supplies th e plls and other peripherals. the system clock input can be connected to either an external oscillator or a crystal using the internal oscillator amplifier. note the internal rtc oscillator does not provide an accurate frequency and is affected by process, voltage, and te mperature variations. nxp strongly recommends using an external crystal as the rtc_xtali reference. if the internal oscillator is used instead, careful considerat ion must be given to the timing implications on all of the soc modules dependent on this clock. gpio supplies 6 nvcc33_io 2.8 3.0 3.3 v worst case, assuming all soc i/o operating at 1.8v. nvcc33_io must always be greater than nvcc18_io. nvcc18_io 1.62 1.8 1.98 v nvcc_1p2v 1.14 1.2 1.3 v junction temperature t j 095 c commercial see i.mx 6sololite product lifetime usage estimates application note , an4726, for information on product lifetime (power-on years) for this processor. junction temperature t j -40 105 extended commercial see i.mx 6sololite product lifetime usage estimates application note , an4726, for information on product lifetime (power-on years) for this processor. 1 applying the maximum voltage results in maximum power cons umption and heat generation. nxp recommends a voltage set point = (vmin + the supply tolerance). this results in an optimized power/speed ratio. 2 vdd_arm_in and vdd_soc_in must be at least 125 mv higher than the ldo output set point for correct voltage regulation. 3 vdd_soc_cap and vdd_pu_cap must be equal. 4 vdd_soc and vdd_pu output voltage must be set to this rule: vdd_arm - vdd_soc / vdd_pu < 50mv. 5 while setting vdd_snvs_in voltage with respect to charging currents and rtc, refer to hardware development guide for i.mx 6dual, 6quad, 6solo, 6duallite families of applications processors (imx6dq6sdlhdg). 6 all digital i/o supplies (nvcc_xxxx) must be powered under normal conditions whether the associated i/o pins are in use or not, and associated i/o pins need to have a pull-up or pu ll-down resistor applied to limit any floating gate current. table 9. operating ranges (continued) parameter description symbol min typ max 1 unit comment
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 23 table 10 shows the interface frequency requirements. the typical values shown in table 10 are required for use with nxp bsps to ensure precise time keeping and usb operation. for rtc_xtali operati on, two clock sources are available: ? on-chip 40 khz ring oscillator: this clock source has the following characteristics: ? approximately 25 a more idd than crystal oscillator ? approximately 50% tolerance ? no external component required ? starts up quicker than 32 khz crystal oscillator ? external crystal os cillator with on-chip support circuit ? at power up, ring oscillator is utilized. after crystal oscill ator is stable, the clock circuit switches over to the crystal oscillator automatically. ? higher accuracy th an ring oscillator ? if no external crystal is present, then the ring oscillator is utilized the decision to choose a clock source should be taken based on real-tim e clock use and precision time-out. 4.1.5 maximum supply currents the power virus numbers shown in table 11 represent a use case designe d specifically to show the maximum current consumption possibl e. all cores are running at the de fined maximum frequency and are limited to l1 cache accesses only to ensure no pi peline stalls. alt hough a valid condition, it would have a very limited practical use case, if at all, and be limited to an extremel y low duty cycle unless the intention was to specifically show the worst case power consumption. the nxp power management ic, mmpf0100xxxx, which is targeted for the i.mx 6 series processor family, supports the power consumption shown in table 11 , however a robust thermal design is required for the increased system power dissipation. see the i.mx 6sololite power consumpti on measurement application note (an4580) for more details on typical power consumption under various use case definitions. table 10. external input clock frequency parameter description symbol min typ max unit rtc_xtali oscillator 1, 2 1 external oscillator or a crystal with internal oscillator amplifier. 2 the required frequency stability of this clock source is application dependent. for recommendations, see hardware development guide for i.mx 6dual, 6quad, 6solo, 6duallit e families of applications processors (imx6dq6sdlhdg). f ckil 3 2 . 7 6 8 (see 3 ) /32.0 3 recommended nominal frequency 32.768 khz. khz xtali oscillator 4, 2 4 external oscillator or a fundamental frequency crystal with internal oscillator amplifier. f xtal 2 4m h z
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 24 nxp semiconductors electrical characteristics table 11. maximum supply currents power line conditions max current unit vdd_arm_in 1 ghz arm clock based on power virus operation 1100 ma vdd_soc_in 1 ghz arm clock 650 ma vdd_pu_in 1 ghz arm clock 150 ma vdd_high_in 30 1 1 the actual maximum current drawn from vdd_high_in will be as shown plus any additional current drawn from the vdd_high_cap outputs, depending upon actual applicatio n configuration (for example, nvcc_dram_2p5 supplies). ma vdd_snvs_in 250 2 2 the maximum vdd_snvs_in current may be higher depending on specific operating configurations, such as boot_mode[1:0] not equal to 00, or use of the tamper feature. during initial power on, vdd_snvs_in can draw up to 1 ma, if available. vdd_snvs_cap charge time will increase if less than 1 ma is available. a usb_otg1_vbus usb_otg2_vbus 25 3 3 this is the maximum current pe r active usb physical interface. ma primary interface (io) supplies nvcc_dram (see 4 ) 4 the dram power consumption is dependent on several factors, such as external signal termination. dram power calculators are typically available from the memory vendors. they take in account factors, such as signal termination. see the i.mx 6sololite power consumpti on measurement application note or examples of dram power consumption during specific use ca se scenarios. nvcc33_io n=156 use maximum io equation 5 5 general equation for estimated, maximum power consumption of an io power supply: imax = n x c x v x (0.5 x f) where: nnumber of io pins supplied by the power line cequivalent external capacitive load vio voltage (0.5 xf)data change rate. up to 0.5 of the clock rate (f) in this equation, imax is in amps, c in farads, v in volts, and f in hertz. nvcc18_io n=156 use maximum io equation 5 nvcc_1p2v n=2 use maximum io equation 5 ma misc dram_vref 1 ma
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 25 4.1.6 low power mode supply currents table 12 shows the current core consumpti on (not including i/o) of i.mx 6sololite processor in selected low power modes. table 12. stop mode current and power consumption mode test conditions supply typical 1 1 the typical values shown here are for information only and are not guaranteed. these values are average values measured on a worst-case wafer at 25 c. unit wait ? arm, soc, and pu ldos are set to 1.225 v ? high ldo set to 2.5 v ? clocks are gated ? ddr is in self refresh ? plls are active in bypass (24 mhz) ? supply voltages remain on vdd_arm_in (1.375 v) 4 ma vdd_soc_in (1.375 v) 7.5 vdd_pu_in (1.375 v) 1.5 vdd_high_in(3.0 v) 9 total 44.9 mw stop_on ? arm ldo set to 0.9 v ? soc and pu ldos set to 1.225 v ? high ldo set to 2.5 v ? plls disabled ? ddr is in self refresh vdd_arm_in (1.375 v) 2.5 ma vdd_soc_in (1.375 v) 7.5 vdd_pu_in (1.375 v) 1.5 vdd_high_in (3.0 v) 4.5 total 29.3 mw stop_off ? arm ldo set to 0.9 v ? soc ldo set to 1.225 v ? pu ldo is power gated ? high ldo set to 2.5 v ? plls disabled ? ddr is in self refresh vdd_arm_in (1.375 v) 2.5 ma vdd_soc_in (1.375 v) 7.5 vdd_pu_in (1.375 v) 0.1 vdd_high_in (3.0 v) 4.0 total 25.9 mw standby ? arm and pu ldos are power gated ? soc ldo is in bypass ? high ldo is set to 2.5 v ? plls are disabled ? low voltage ? well bias on ? xtal is enabled vdd_arm_in (0.9 v) 0.1 ma vdd_soc_in (0.9 v) 1.0 vdd_pu_in (0.9 v) 0.1 vdd_high_in (3.0 v) 3 total 10.1 mw deep sleep mode (dsm) ? arm and pu ldos are power gated ? soc ldo is in bypass ? high ldo is set to 2.5 v ? plls are disabled ? low voltage ? well bias on ? xtal and bandgap are disabled vdd_arm_in (0.9 v) 0.1 ma vdd_soc_in (0.9 v) 0.75 vdd_pu_in (0.9 v) 0.1 vdd_high_in (3.0 v) 0.15 to t a l 1 . 3 m w snvs only ? vdd_snvs_in powered ? all other supplies off ? srtc running vdd_snvs_in (2.8v) 41 a to t a l 1 1 5 w
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 26 nxp semiconductors electrical characteristics 4.1.7 usb phy current consumption 4.1.7.1 power down mode in power down mode, everything is powered down, including the usb_otgx_vbus valid detectors, typical condition. table 13 shows the usb interface current consumption in power down mode. note the currents on the vdd_high_ cap and vdd_usb_cap were identified to be the voltage divider circuits in the usb-specific level shifters. 4.2 power supplies requir ements and restrictions the system design must comply with power-up sequence, power-down seque nce, and steady state guidelines as described in this section to guarantee the reliable operation of the device. any deviation from these sequences may result in the following situations: ? excessive current during power-up phase ? prevention of the device from booting ? irreversible damage to the pr ocessor (worst-case scenario) 4.2.1 power-up sequence for power-up sequence, the re strictions are as follows: ? vdd_snvs_in supply must be tu rned on before any other power supply. it may be connected (shorted) with vdd_high_in supply. ? if a coin cell is used to power vdd_snvs_in, then ensure that it is connected before any other supply is switched on. ? src_por_b signal is used to control the processor por. src_por_b must be immediately asserted at power-up and remain asserted until the vdd_arm_cap, vdd_soc_cap, and vdd_pu_cap supplies are stable . vdd_arm_in and vdd_soc_in may be applied in either order with no restrictions. note ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 v supply (for example, from the external components that use both the 1.8 v and 3.3 v supplies). note usb_otg_vbus and usb_h1_vbus ar e not part of the power supply sequence and can be powered at any time. table 13. usb phy current consumption in power down mode vdd_usb_cap (3.0 v) vddhigh_cap (2.5 v) nvcc_pll_out (1.1 v) current 5.1 a1.7 a <0.5 a
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 27 note for customers beginning new designs with the i.mx 6sololite and the pf0100 pmic, it is recommended to us e the f3 otp option instead of the f1 otp option and the f4 otp option instead of the f2 otp option. 4.2.2 power-down sequence there are no special requirements on the power-down sequence other than the vdd_snvs_in supply should be the last to turn off. 4.2.3 power supplies usage all i/o pins should not be externally driven while the i/o power supply for the pin (nvcc_xxx) is off. this can cause internal latch-up a nd malfunctions due to reverse curren t flows. for info rmation about i/o power supply of each pin, s ee ?power group? column of table 66, "13 x 13 mm functional contact assignments," on page 86 . 4.3 integrated ldo voltage regulator parameters various internal supplies can be powered on from inte rnal ldo voltage regulators. all the supply pins named *_cap must be connected to external capaci tors. the onboard ldos are intended for internal use only and should not be used to power any external circuitry. see the i.mx 6sololite reference manual for details on the power tree scheme recommended operation. note the *_cap signals should not be power ed externally. these signals are intended for internal ldo or ldo bypass operation only. 4.3.1 digital regulators (ldo_arm, ldo_pu, ldo_soc) there are three digital ldo regulators (?digital?, beca use of the logic loads that they drive, not because of their construction). the advantages of the regulator s are to reduce the input s upply variation because of their input supply ripple re jection and their on die tr imming. this translates into more voltage for the die producing higher operating frequencies. these regulators have three basic modes. ? bypass. the regulation fet is switched fully on passing the exte rnal voltage, dcdc_low, to the load unaltered. the analog part of the regulator is powered down in this state, removing any loss other than the ir drop through the power grid and fet. ? power gate. the regulation fet is switched fully off limiting the current draw from the supply. the analog part of the regulator is powered down here limiting the power consumption. ? analog regulation mode. the regulation fet is controlled such that the output voltage of the regulator equals the programmed ta rget voltage. the target voltage is fully programmable in 25 mv steps. for additional information, see the i.mx 6sololite reference manual.
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 28 nxp semiconductors electrical characteristics 4.3.2 regulators for analog modules 4.3.2.1 ldo_1p1 the ldo_1p1 regulator implements a programmable linear-regulator function from vdd_high_in (see table 9 for min and max input require ments). typical programming operating range is 1.0 v to 1.2 v with the nominal default setting as 1.1 v. ldo_1p1 supplies the us b phy and the plls. a programmable brown-out detector is include d in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded to take the necessary steps. current-limiting can be enabled to allow for in-rush curren t requirements during start-up, if needed. active-pull- down can also be enabled for systems requiring this feature. for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx 6sololite applica tions processors (imx6slhdg). fo r additional information, see the i.mx 6sololite reference manual. 4.3.2.2 ldo_2p5 the ldo_2p5 module implements a programmable linear-regulator function from vdd_high_in (see table 9 for minimum and maximum input requirement s). typical programming operating range is 2.25 v to 2.75 v with the nominal default setting as 2.5 v. ldo_2p5 supplies the usb phy, lvds phy and plls. a programmable brown-out detector is included in the regul ator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. current-limiting can be enabled to allow for in-r ush current requirements during start-up, if needed. active-pull-down can also be enab led for systems requiring this feat ure. an alternate self-biased low-precision weak-regulator is included that can be enabled for applications needing to keep the output voltage alive during low-power modes where the main re gulator driver and its associated global bandgap reference module are disabled. the output of the weak -regulator is not programmable and is a function of the input supply as well as the load current. typically, with a 3 v input supply the weak-regulator output is 2.525 v and its output impedance is approximately 40 . for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx 6sololite applic ations processors (imx6slhdg). for additional information, see the i.mx 6sololite reference manual. 4.3.2.3 ldo_usb the ldo_usb module implements a program mable linear-regulator function from the usb_otg1_vbus and usb_otg2_vbu s voltages (4.4 v?5.25 v) to produce a nominal 3.0 v output voltage. a programmable brown-out det ector is included in the regulator that can be used by the system to determine when the load capability of the regulator is be ing exceeded, to take the necessary steps. this regulator has a built in power-mux that allows the user to select to run the re gulator from either vbus supply, when both are present. if only one of th e vbus voltages is presen t, then, the regulator automatically selects this supply. current limit is al so included to help the system meet in-rush current targets. if no vbus voltage is present, then the vbusvalid threshold setting will prevent the regulator from being enabled.
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 29 for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx 6sololite applic ations processors (imx6slhdg). for additional information, see the i.mx 6sololite reference manual. 4.4 pll?s electrical characteristics 4.4.1 audio/video pll?s electrical parameters 4.4.2 528 mhz pll 4.4.3 ethernet pll table 14. audio/video pll?s electrical parameters parameter value clock output range 650 mhz ~1.3 ghz reference clock 24 mhz lock time <11250 reference cycles (450 s) table 15. 528 mhz pll?s electrical parameters parameter value clock output range 528 mhz pll output reference clock 24 mhz lock time <11250 reference cycles (15 s) table 16. ethernet pll?s electrical parameters parameter value clock output range 500 mhz reference clock 24 mhz lock time <11250 reference cycles (450 s)
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 30 nxp semiconductors electrical characteristics 4.4.4 480 mhz pll 4.4.5 arm pll 4.5 on-chip oscillators 4.5.1 osc24m this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements an oscillator. it also implem ents a power mux such that the oscillator can be powered from nvcc_1p2v or vdd_soc. nvcc_1p2v should be the cleaner supply and is the preferable choice, however, if the oscillator is required to run in stop mode then it is necessary to run from vdd_soc, which is 0.9 v in stop mode. the system crystal oscillator consists of a pierce-t ype structure running off the digital supply. a straight forward biased-inverter implementation is used. 4.5.2 osc32k this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements a low power oscillator. it also implements a power mux such that it can be powered from either a ~3 v backup battery (vdd_snvs_in) or vdd_high_in such as the oscillator consumes power from vdd_high_in when that supply is available and transitions to the back up battery when vdd_high_in is lost. in addition, if the clock monitor dete rmines that the osc32k is not pres ent, then the source of the 32 khz clock will automatically switch to the internal ring oscillator. table 17. 480 mhz pll?s electrical parameters parameter value clock output range 480 mhz pll output reference clock 24 mhz lock time <383 reference cycles (15 s) table 18. arm pll?s electrical parameters parameter value clock output range 650 mhz~1.3 ghz reference clock 24 mhz lock time <2250 reference cycles (50 s)
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 31 caution the internal rtc oscillator does not provide an accurate frequency and is affected by process, voltage and te mperature variations. nxp strongly recommends using an external crystal as the rtc_xtali reference. if the internal oscillator is used instead, careful considerat ion must be given to the timing implications on all of the soc modules dependent on this clock. the osc32k runs from vdd_snvs_cap, which comes from the vdd_high_in/vdd_snvs_in power mux. 4.6 i/o dc parameters this section includes the dc parameters of the following i/o types: ? dual voltage general purpos e i/o cell set (dvgpio) ? double data rate i/o (ddr) for lpddr2 and ddr3 modes note the term ovdd in this section refers to the associated supply rail of an input or output. table 19. osc32k main characteristics parameter min typ max comments fosc 32.768 khz this frequency is nominal and determined mainly by the crystal selected. 32.0 k would work as well. current consumption 4 a the typical value shown is only for the oscillator, driven by an external crystal. if the internal ring oscillator is used instead of an external crystal, then approximately 25 a should be added to this value. bias resistor 14 m this the integrated bias resistor that sets the amplifier into a high gain state. any leakage through the esd network, external board leakage, or even a scope probe that is significant relative to this value will debias the amp. the debiasing will result in low gain, and will impact the circuit's ability to start up and maintain oscillations. target crystal properties cload 10 pf usually crystals can be purchased tuned for different cloads. this cload value is typically 1/2 of the capacitanc es realized on the pcb on either side of the quartz. a higher cload will decr ease oscillation margin, but increases current oscillating through the crystal. esr 50 k equivalent series resistance of the crystal. choosing a crystal with a higher value will decrease the oscillating margin.
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 32 nxp semiconductors electrical characteristics figure 4. circuit for parameters voh and vol for i/o cells 4.6.1 xtali and rtc_xtali (clock inputs) dc parameters table 20 shows the dc parameters for the clock inputs. note the vil and vih specifications only appl y when an external clock source is used. if a crystal is used, vil and vih do not apply. 4.6.2 dual voltage general purpose io cell set (dvgpio) dc parameters table 21 shows dc parameters for gp io pads. the parameters in table 21 are guaranteed per the operating ranges in table 9 , unless otherwise noted. table 20. xtali and rtc_xtali dc parameters parameter symbol test conditions min typ max unit xtali high-level dc input voltage vih 0.8 x nvcc_pll_out nvcc_pll_ out v xtali low-level dc input voltage vil 0 0.2v v rtc_xtali high-level dc input voltage vih 0.8 1.1 1 1 this voltage specification must not be exceeded and, as such, is an absolute maximum specification. v rtc_xtali low-level dc input voltage vil 0 0.2v v input capacitance c in simulated data 5 pf xtali input leakage at startup i xtali_startup power-on startup for 0.15 msec with a driven 24 mhz rtc clock @1.1 v. 2 2 this current draw is present even if an external clock source directly drives xtali. 600 a dc input current i xtali_dc 2 . 5 a 0 or 1 predriver pdat ovdd pad nmos (rpd) ovss voh min vol m ax pmos (rpu)
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 33 4.6.3 ddr i/o dc parameters the ddr i/o pads support lpddr2 and ddr3 operational modes. 4.6.3.1 lpddr2 mode i/o dc parameters the parameters in table 22 are guaranteed per the operating ranges in table 9 , unless otherwise noted. for details on supported ddr memory configurations, see section 4.9.4, ?multi-mode ddr controller (mmdc) ?. table 21. dvgpio i/o dc parameters parameter symbol test conditions min max unit high-level output voltage 1 1 overshoot and undershoot conditions (tr ansitions above ovdd and below gnd) on switching pads must be held below 0.6 v, and the duration of the oversh oot/undershoot must not exceed 10% of the system cloc k cycle. overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. non-compliance to this specification may affect de vice reliability or cause permanent damage to the device. voh ioh = -0.1 ma (dse 2 = 001, 010) ioh = -1 ma (dse = 011, 100, 101, 110, 111) 2 dse is the drive strength field setting in the associated iomux control register. ovdd C 0.15 v low-level output voltage 1 vol iol = 0.1 ma (dse 2 = 001, 010) iol = 1ma (dse = 011, 100, 101, 110, 111) 0.15v high-level dc input voltage 1, 3 3 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. vih 0.7 ovdd ovdd v low-level dc input voltage 1, 3 vil 0 0.3 ovdd v input hysteresis vhys ovdd = 1.8 v ovdd = 3.3 v 0.25 v schmitt trigger vt+ , 3, 4 4 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. vt+ 0.5 ovdd v schmitt trigger vtC , 3, 4 vtC 0.5 ovdd v input current (no pull-up/down ) iin vin = ovdd or 0 -1.25 1.25 a input current (22 k pull-up) iin vin = 0 v vin = ovdd 2 1 2 1 a input current (47 k pull-up) iin vin = 0 v vin = ovdd 1 0 0 1 a input current (100 k pull-up) iin vin = 0 v vin= ovdd 4 8 1 a input current (100 k pull-down) iin vin = 0 v vin = ovdd 1 48 a keeper circuit resistance rkeep vin = 0.3 x ovdd vin = 0.7 x ovdd 105 205 k
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 34 nxp semiconductors electrical characteristics 4.6.3.2 ddr3 mode i/o dc parameters the parameters in table 23 are guaranteed per the operating ranges in table 9 , unless otherwise noted. for details on supported ddr memory configurations, see section 4.9.4, ?multi-mode ddr controller (mmdc) ?. table 22. lpddr2 i/o dc electrical parameters 1 1 note that the jedec lpddr2 specification (jesd209_ 2b) supersedes any specification in this document. parameters symbol test conditions min max unit high-level output voltage voh ioh = -0.1 ma 0.9 ovdd v low-level output voltage vol iol = 0.1 ma 0.1 ovdd v input reference voltage vref 0.49 ovdd 0.51 ovdd v dc input high voltage vih(dc) vref+0.13v ovdd v dc input low voltage vil(dc) ovss vref-0.13v v differential input logic high vih(diff) 0.26 see note 2 2 the single-ended signals need to be within the respective limits (vih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot (see ta b l e 2 6 ). v differential input logic low vil(diff) see note 2 -0.26 v input current (no pull-up/down) iin vin = 0 or ovdd -2.5 2.5 a pull-up/pull-down impedance mismatch mmpupd -15 +15 % 240 unit calibration resolution rres 10 keeper circuit resistance rkeep 110 175 k table 23. ddr3 i/o dc electrical parameters 1 parameters symbol test conditions min max unit high-level output voltage voh ioh = -0.1 ma voh (dse = 001) 0.8 ovdd 2 v ioh = -1 ma voh (for all except dse = 001) low-level output voltage vol iol = 0.1 ma vol (dse = 001) 0.2 ovdd v iol = 1 ma vol (for all except dse = 001) input reference voltage vref 3 0 . 4 9 ovdd 0.51 ovdd dc input logic high vih(dc) vref+0.1 ovdd v dc input logic low vil(dc) ovss vref-0.1 v differential input logic high vih(diff) 0.2 see note 4 v differential input logic low vil(diff) see note 4 -0.2 v termination voltage vtt vtt tracking ovdd/2 0.49 ovdd 0.51 ovdd v
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 35 4.7 i/o ac parameters this section includes the ac parameters of the following i/o types: ? general purpose i/o (gpio) ? dual voltage general purpose i/o (dvgpio) ? double data rate i/o (ddr) for lpddr2 and ddr3 modes the gpio and ddr i/o load circuit and out put transition time waveforms are shown in figure 5 and figure 6 . figure 5. load circuit for output figure 6. output transition time waveform input current (no pull-up/dow n) iin vin = 0 or ovdd -2.9 2.9 a pull-up/pull-down impedance mismatch mmpupd - 1 01 0 % 240 unit calibration resolution rres 10 keeper circuit resistance 5 rkeep 105 175 k 1 note that the jedec ddr3 specification (jesd79_3d) supersedes any specification in this document. 2 ovdd C i/o power supply (1.425 v C 1.575 v for ddr3 3 vref C ddr3 external reference voltage 4 the single-ended signals need to be within the respective limits (vih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot (see ta b l e 2 7 ). 5 use an off-chip pull resistor of 10 k or less to override this keeper. table 23. ddr3 i/o dc electrical parameters 1 (continued) parameters symbol test conditions min max unit test point from output cl cl includes package, probe and fixture capacitance under test 0v ovdd 20% 80% 80% 20% tr tf output (at pad)
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 36 nxp semiconductors electrical characteristics 4.7.1 general purpose i/o ac parameters the i/o ac parameters for gpio in slow and fast modes are presented in the table 24 and table 25 , respectively. note that the fast or slow i/o behavior is determined by the appropriate control bits in the iomuxc control registers. table 24. general purpose i/o ac parameters 1.8 v mode parameter symbol test condition min typ max unit output pad transition times, rise/fall (max drive, ipp_dse=111) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate 2.72/2.79 1.51/1.54 ns output pad transition times, rise/fall (high drive, ipp_dse=101) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate 3.20/3.36 1.96/2.07 output pad transition times, rise/fall (medium drive, ipp_dse=100) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate 3.64/3.88 2.27/2.53 output pad transition times, rise/fall (low drive. ipp_dse=011) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate 4.32/4.50 3.16/3.17 input transition times 1 1 hysteresis mode is recommended for input s with transition times greater than 25 ns. trm 25 ns table 25. general purpose i/o ac parameters 3.3 v mode parameter symbol test condition min typ max unit output pad transition times, rise/fall (max drive, ipp_dse=101) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate 1.70/1.79 1.06/1.15 ns output pad transition times, rise/fall (high drive, ipp_dse=011) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate 2.35/2.43 1.74/1.77 output pad transition times, rise/fall (medium drive, ipp_dse=010) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate 3.13/3.29 2.46/2.60 output pad transition times, rise/fall (low drive. ipp_dse=001) tr, tf 15 pf cload, slow slew rate 15 pf cload, fast slew rate 5.14/5.57 4.77/5.15 input transition times 1 1 hysteresis mode is recommended for inputs with transition times greater than 25 ns. trm 25 ns
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 37 4.7.2 ddr i/o ac parameters table 26 shows the ac parameters for ddr i/o opera ting in lpddr2 mode. for details on supported ddr memory configurations, see section 4.9.4, ?multi-mode ddr controller (mmdc) ?. table 27 shows the ac parameters for ddr i/o operating in ddr3 mode. table 26. ddr i/o lpddr2 mode ac parameters 1 1 note that the jedec lpddr2 specification (jesd209_2b ) supersedes any specification in this document. parameter symbol test condition min typ max unit ac input logic high vih(ac) vref + 0.22 ovdd v ac input logic low vil(ac) 0 vref C 0.22 v ac differential input high voltage 2 2 vid(ac) specifies the input differential voltage |vtr C vcp| requir ed for switching, where vtr is t he true input signal and vcp is the complementary input signal. the mini mum value is equal to vih(ac) C vil(ac). vidh(ac) 0.44 v ac differential input low voltage vidl(ac) 0.44 v input ac differential cross point voltage 3 3 the typical value of vix(ac) is expected to be about 0.5 ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which diff erential input signal must cross. vix(ac) relative to vref -0.12 0.12 v over/undershoot peak vpeak 0.35 v over/undershoot area (above ovdd or below ovss) varea 400 mhz 0.3 v-ns single output slew rate, measured between vol (ac) and voh (ac) tsr 50 to vref. 5 pf load. drive impedance = 4 0 30% 1.5 3.5 v/ns 50 to vref. 5pf load. drive impedance = 60 30% 12.5 skew between pad rise/fall asymmetry + skew caused by ssn t skd clk = 400 mhz 0.1 ns table 27. ddr i/o ddr3 mode ac parameters 1 parameter symbol test condition min typ max unit ac input logic high vih(ac) vref + 0.175 ovdd v ac input logic low vil(ac) 0 vref C 0.175 v ac differential input voltage 2 vid(ac) 0.35 v input ac differential cross point voltage 3 vix(ac) relative to vref vref C 0.15 vref + 0.15 v over/undershoot peak vpeak 0.4 v over/undershoot area (above ovdd or below ovss) varea 400 mhz 0.5 v-ns
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 38 nxp semiconductors electrical characteristics 4.8 output buffer impedance parameters this section defines the i/o impeda nce parameters of the i.mx 6sololite processor for the following i/o types: ? dual voltage general purpose i/o cell set (dvgpio) ? double data rate i/o (ddr) for lpddr2, and ddr3 modes note gpio and ddr i/o output driver imp edance is measured with ?long? transmission line of impeda nce ztl attached to i/o pad and incident wave launched into transmission line. rpu/rpd and ztl form a volta ge divider that defines specific voltage of incident wave relative to ovdd. output driver impedance is calculated from this voltage divider (see figure 7 ). single output slew rate, measured between vol (ac) and voh (ac) tsr driver impedance = 34 2.5 5 v/ns skew between pad rise/fall asymmetry + skew caused by ssn t skd clk = 400 mhz 0.1 ns 1 note that the jedec jesd79_3c specification su persedes any specification in this document. 2 vid(ac) specifies the input differential voltage |vtr-vcp| requir ed for switching, where vtr is the true input signal and vcp is the complementary input signal. the minimum value is equal to vih(ac) C vil(ac). 3 the typical value of vix(ac) is expected to be about 0.5 ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. table 27. ddr i/o ddr3 mode ac parameters 1 (continued) parameter symbol test condition min typ max unit
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 39 figure 7. impedance matching load for measurement 4.8.1 dual voltage gpio output buffer impedance table 28 shows the gpio output buffer impedance (ovdd 1.8 v). table 28. dvgpio output buffer average impedance (ovdd 1.8 v) parameter symbol drive streng th (ipp_dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 262 134 88 62 51 43 37 ipp_do cload = 1p ztl , l = 20 inches predriver pmos (rpu) nmos (rpd) pad ovdd ovss t,(ns) u,(v) ovdd t,(ns) 0 vdd vin (do) vout (pad) u,(v) vref rpu = vovddCvref1 vref1 ztl rpd = ztl vref2 vovddCvref2 vref1 vref2 0
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 40 nxp semiconductors electrical characteristics table 29 shows the gpio output buffer impedance (ovdd 3.3 v). 4.8.2 ddr i/o output buffer impedance for details on supported ddr me mory configurations, see section 4.9.4, ?multi-mod e ddr controller (mmdc) .? table 30 shows ddr i/o output buffer impeda nce of i.mx 6sololite processor. note: 1. output driver impedanc e is controlled across pvts using zq calibration procedure. 2. calibration is done against 240 w external reference resistor. 3. output driver impedance devi ation (calibration accuracy) is 5% (max/min impedance) across pvts. 4.9 system modules timing this section contains the timing and electrical pa rameters for the modules in each i.mx 6sololite processor. table 29. dvgpio output buffer average impedance (ovdd 3.3 v) parameter symbol drive streng th (ipp_dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 247 126 84 57 47 40 34 table 30. ddr i/o output buffer impedance parameter symbol test conditions typical unit nvcc_dram=1.5 v (ddr3) ddr_sel=11 nvcc_dram=1.2 v (lpddr2) ddr_sel=10 output driver impedance rdrv drive strength (dse) = 000 001 010 011 100 101 110 111 hi-z 240 120 80 60 48 40 34 hi-z 240 120 80 60 48 40 34
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 41 4.9.1 reset timings parameters figure 8 shows the reset timing and table 31 lists the timing parameters. figure 8. reset timing diagram 4.9.2 wdog reset timing parameters figure 9 shows the wdog reset timing and table 32 lists the timing parameters. figure 9. wdog_b timing diagram note rtc_xtali is approximately 32 khz. rtc_xtali cycle is one period or approximately 30 s. note wdog_b output signals (for each one of the watchdog modules) do not have dedicated bins, but are muxed out through the iomux. see the iomux manual for detailed information. table 31. reset timing parameters id parameter min max unit cc1 duration of por_b to be qualified as valid. 1 xtalosc_rtc_xtali table 32. wdog_b timing parameters id parameter min max unit cc3 duration of wdog_b assertion 1 rtc_xtali cycle src_por_b cc1 (input) wdog_b cc3 (output)
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 42 nxp semiconductors electrical characteristics 4.9.3 external interface module (eim) the following subsections provide information on the eim. the maximum operating frequency for eim data transfer is 104 mhz. ti ming parameters in this sect ion that are given as a func tion of register settings or clock periods are valid for the entire range of allowed fr equencies (0?104 mhz). 4.9.3.1 eim interface pads allocation eim supports 32-bit, 16-bit, and 8-bi t devices operating in address/data separate or multiplexed modes. table 33 provides eim interface pads al location in different modes. table 33. eim internal module multiplexing 1 1 for more information on configuration ports mentioned in this table, see the i.mx 6solollite reference manual. setup non multiplexed address/data mode multiplexed address/data mode 8 bit 16 bit 16 bit 32 bit mum = 0, dsz = 100 mum = 0, dsz = 101 mum = 0, dsz = 001 mum = 1, dsz = 001 mum = 1, dsz = 011 eim_addr [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_ad [15:00] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_addr [25:16] eim_data [09:00] eim_data [07:00], eim_eb0_b eim_data [07:00] e i m _ d a t a [07:00] eim_ad [07:00] eim_ad [07:00] eim_data [15:08], eim_eb1_b e i m _ d a t a [15:08] eim_data [15:08] eim_ad [15:08] eim_ad [15:08] eim_data [23:16], eim_eb2_b e i m _ d a t a [07:00] eim_data [31:24], eim_eb3_b e i m _ d a t a [15:08]
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 43 4.9.3.2 general eim timing-synchronous mode figure 10 , figure 11 , and table 34 specify the timings related to th e eim module. all eim output control signals may be asserted and deasserted by an in ternal clock synchronized to the bclk rising edge according to corresponding assert ion/negation control fields. , figure 10. eim output timing diagram figure 11. eim input timing diagram 4.9.3.3 examples of eim synchronous accesses table 34. eim bus timing parameters id parameter min 1 max 1 unit we1 eim_bclk cycle time 2 t (k+1) ns we2 eim_bclk high level width 0.4 t (k+1) ns we3 eim_bclk low level width 0.4 t (k+1) ns we4 clock rise to address valid -0.5 t (k+1) -1.25 -0.5 t (k+1) +2.25 ns we4 eim_addr eim_csx_b eim_rw_b eim_oe_b eim_bclk eim_ebx_b eim_lba_b output data we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we15 we16 we17 we3 we2 we1 input data eim_wait_b eim_bclk we19 we18 we21 we20
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 44 nxp semiconductors electrical characteristics we5 clock rise to address invalid 0.5 t (k+1) -1.25 0.5 t (k+1) +2.25 ns we6 clock rise to eim_csx_b valid -0.5 t (k+1) -1.25 -0.5 t (k+1) +2.25 ns we7 clock rise to eim_csx_b invalid 0.5 t (k+1) -1.25 0.5 t (k+1) +2.25 ns we8 clock rise to eim_rw_b valid -0.5 t (k+1) -1.25 -0.5 t (k+1) +2.25 ns we9 clock rise to eim_rw_b invalid 0.5 t (k+1) -1.25 0.5 t (k+1) +2.25 ns we10 clock rise to eim_oe_b valid -0.5 t (k+1) -1.25 -0.5 t (k+1) +2.25 ns we11 clock rise to eim_oe_b invalid 0.5 t (k+1) -1.25 0.5 t (k+1) +2.25 ns we12 clock rise to eim_ebx_b valid 0.5 t (k+1) -1.25 -0.5 t (k+1) +2.25 ns we13 clock rise to eim_ebx_b invalid 0.5 t (k+1) -1.25 0.5 t (k+1) +2.25 ns we14 clock rise to eim_lba_b valid -0.5 t (k+1) -1.25 -0.5 t (k+1) +2.25 ns we15 clock rise to eim_lba_b invalid 0.5 t (k+1) -1.25 0.5 t (k+1) +2.25 ns we16 clock rise to output data valid -0.5 t ( k+1) -1.25 -0.5 t (k+1) +2.25 ns we17 clock rise to output data invalid 0.5 t (k+1) -1.25 0.5 t (k+1) +2.25 ns we18 input data setup time to clock rise 2.3 ns we19 input data hold time from clock rise 2 ns we20 eim_wait_b setup time to clock rise 2 ns we21 eim_wait_b hold time from clock rise 2 ns 1 k represents register setting bcd value 2 t is clock period (1/freq). for 104 mhz, t = 9.165 ns table 34. eim bus timing parameters (continued) id parameter min 1 max 1 unit
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 45 figure 12 to figure 15 provide few examples of ba sic eim accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings. figure 12. synchronous memory read access, wsc=1 figure 13. synchronous memory, write access, wsc=1, wbea=0, and wadvn=0 last valid address address v1 d(v1) eim_bclk eim_addrxx eim_dataxx eim_rw_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b we4 we5 we6 we7 we10 we11 we13 we12 we14 we15 we18 we19 last valid address address v1 d(v1) eim_bclk eim_addrxx eim_dataxx eim_rw_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b we4 we5 we6 we7 we8 we9 we12 we13 we14 we15 we16 we17
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 46 nxp semiconductors electrical characteristics figure 14. muxed address/data (a/d) mode, synchronous write access, wsc=6, adva=0, advn=1, and adh=1 note in 32-bit muxed address/data (a/d) mode the 16 msbs are driven on the data bus. figure 15. 16-bit muxed a/d mode , synchronous read access, wsc=7, radvn=1, adh=1, oea=0 4.9.3.4 general eim timing-asynchronous mode figure 16 through figure 20 , and table 35 help you determine timing parame ters relative to the chip select (cs) state for asynchronous and dtack eim accesses with corresponding eim bit fields and the timing parameters mentioned above. asynchronous read and write acce ss length in cycles may vary from what is shown in figure 16 through figure 19 as rwsc, oen and csn is configured differe ntly. see the i.mx 6sololite reference manual for the eim programming model. eim_bclk eim_addrxx/ eim_rw_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b address v1 write data eim_dataxx we4 we16 we6 we7 we9 we8 we10 we11 we14 we15 we17 we5 last address valid we4 last eim_bclk eim_addrxx/ eim_rw_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b address v1 data address eim_dataxx we5 we6 we7 we14 we15 we10 we11 we12 we13 we18 we19 valid
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 47 figure 16. asynchronous memory read access (rwsc = 5) figure 17. asynchronous a/d muxed read access (rwsc = 5) last valid address address v1 d(v1) eim_addrxx/ eim_data[7:0] eim_rw_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we39 we35 we37 we32 we36 we38 we40 we31 we44 internal start of access end of access maxdi maxcso maxco eim_dataxx clock we43 addr. v1 d(v1) eim_addrxx/ eim_rw_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b we39 we35a we37 we36 we38 we40a we31 we44 internal start of access end of access maxdi maxcso maxco we32a eim_dataxx clock
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 48 nxp semiconductors electrical characteristics figure 18. asynchronous memory write access figure 19. asynchronous a/d muxed write access last valid address address v1 d(v1) eim_addrxx eim_dataxx eim_rw_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41 eim_rw_b eim_oe_b eim_ebx_b eim_csx_b we33 we45 we34 we46 addr. v1 d(v1) eim_addrxx/ we31 we42 we41a we32a eim_dataxx eim_lba_b we39 we40a
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 49 figure 20. dtack read access (dap=0) figure 21. dtack write access (dap=0) last valid address address v1 d(v1) eim_addrxx eim_data[7:0] eim_rw_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 eim_dtack_b we47 we48 last valid address address v1 d(v1) eim_addrxx eim_dataxx eim_rw_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41 eim_dtack_b we47 we48
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 50 nxp semiconductors electrical characteristics table 35. eim asynchronous timing parameters table relative chip select reference number parameter determination by synchronous measured parameters 1 min max unit we31 eim_csx_b valid to address valid we4-we6-csat 2 -3.5-csat 3.5-csat ns we32 address invalid to eim_csx_b invalid we7-we5-csnt 3 -3.5-csnt 3.5-csnt ns we32a (muxed a/d) eim_csx_b valid to address invalid t 4 +we4-we7+ (advn+adva+1-csa 2,5,6 ) t t - 3.5 + (advn + adva + 1 - csa)t t + 3.5 + (advn + adva + 1 - csa)t ns we33 eim_csx_b valid to eim_rw_we_b valid we8-we6+(wea-wcsa) t -3.5+(wea-wcs a)t 3.5+(wea-csa)t ns we34 eim_we_b invalid to eim_csx_b invalid we7-we9+(wen-wcsn) t -3.5+(wen-wcs n)t 3.5-(wen-wcsn)t ns we35 eim_csx_b valid to eim_oe_b valid we10-we6+(oea-rcsa) t -3.5+(oea-rcs a)t 3.5+(oea-rcsa)t ns we35a (muxed a/d) eim_csx_b valid to eim_oe_b valid we10-we6+(oea+radv n+radva+adh+1-rcsa) t -3.5 + (oea + radvn+radva+ adh+1-rcsa)t 3.5+(oea+radvn+ radva+adh+1- rcsa)t ns we36 eim_oe_b invalid to eim_csx_b invalid we7-we11+(oen-rcsn) t -3.5+(oen-rcs n)t 3.5+(oen-rcsn)t ns we37 eim_csx_b valid to eim_ebx_b valid (read access) we12-we6+(rbea- rcsa)t -3.5+(rbea- rc sa)t 3.5+(rbea 7 -rcsa)t ns we38 eim_ebx_b invalid to eim_csx_b invalid (read access) we7-we13+(rben-rcsn) t -3.5+(rben-rcs n)t 3.5+(rben-rcsn)t ns we39 eim_csx_b valid to eim_lba_b valid we14-we6+(adva-csa)t -3.5+(adva-csa) t 3.5+(adva-csa)t ns we40 eim_lba_b invalid to eim_csx_b invalid (advl is asserted) we7-we15-csnt -3.5-csnt 3.5-csnt ns we40a (muxed a/d) eim_csx_b valid to eim_lba_b invalid we14-we6+(advn+adva+ 1-csa)t -3.5+(advn+ad va+1-csa)t 3.5+(advn+adva +1-csa)t ns we41 eim_csx_b valid to output data valid we16-we6-wcsat -3.5-wcsat 3.5-wcsat ns we41a (muxed a/d) eim_csx_b valid to output data valid we16-we6+(wadvn+wad va+adh+1-wcsa)t -3.5+(wadvn+ wadva +adh+1-wcsa) t 3.5+(wadvn+wadva +adh+1-wcsa)t ns we42 output data invalid to eim_csx_b invalid we17-we7-csnt -3.5-csnt 3.5-csnt ns
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 51 maxco output maximum delay from internal driving eim_addrxx/contro l flip-flops to chip outputs. 10 10 ns maxcso output maximum delay from internal chip selects driving flip-flops to eim_csx_b out. 10 10 ns maxdi eim_dataxx maximum delay from chip input data to its internal flip-flop 55n s we43 input data valid to eim_csx_b invalid maxco-maxcso+maxdi maxco-maxcs o+maxdi n s we44 eim_csx_b invalid to input data invalid 00n s we45 eim_csx_b valid to eim_ebx_b valid (write access) we12-we6+(wbea- wcsa)t -3.5+(wbea- wcsa)t 3.5+(wbea-wcsa)t ns we46 eim_ebx_b invalid to eim_csx_b invalid (write access) we7-we13+(wben- wcsn)t -3.5+(wben-wc sn)t 3.5+(wben-wcsn)t ns maxdti maximum delay from eim_dtack_b input to its internal flip-flop + 2 cycles for synchronization 10 10 ns we47 eim_dtack_b active to eim_csx_b invalid maxco-maxcso+maxdti maxco-maxcs o+maxdti n s we48 eim_csx_b invalid to eim_dtack_b invalid 00n s 1 for more information on configuration pa rameters mentioned in this table, s ee the i.mx 6sololite reference manual. 2 csa means register setting for wcsa when in wr ite operations or rcsa when in read operations. 3 csn means register setting for wcsn when in write operations or rcsn when in read operations. 4 t means clock period from axi_clk frequency. 5 adva means register setting for wadva when in write operations or radva when in read operations. 6 advn means register setting for wadvn when in writ e operations or radvn when in read operations. 7 beassertion.thisbitfielddetermineswhenbesignalisassertedduringreadcycles. table 35. eim asynchronous timing parameters table relative chip select (continued) reference number parameter determination by synchronous measured parameters 1 min max unit
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 52 nxp semiconductors electrical characteristics 4.9.4 multi-mode ddr controller (mmdc) the multi-mode ddr controller is a de dicated interface to ddr3/lpddr2 sdram. 4.9.4.1 mmdc compatibility with jedec-compliant sdrams the i.mx 6sololite mmdc is compatible with the following jedec-compliant memory types: ? lpddr2 sdram compliant to jesd209-2b lp ddr2 jedec standard release june, 2009 ? ddr3 sdram compliant to jesd79-3d ddr 3 jedec standard release april, 2008 mmdc operation with the standards stated above is contingent upon th e board ddr design adherence to the ddr design and layout requirements stated in the hardware development guide for i.mx 6sololite applications processors (imxslhdg). 4.9.4.2 mmdc supported ddr3/lpddr2 configurations table 36 shows the supported ddr3/lpddr2 configurations. 4.10 external peripheral interface parameters the following subsections provide information on external peripheral interfaces. 4.10.1 audmux timing parameters the audmux provides a programmable interconnect logic for voice, a udio, and data routing between internal serial interfaces (ssis) and external serial interfaces (audio and voice codecs). the ac timing of audmux external pins is governed by the ssi module. for more information, see the respective ssi electrical specifications f ound within this document. 4.10.2 cmos sensor interface (csi) timing parameters 4.10.2.0.1 gated clock mode timing figure 22 and figure 23 shows the gated clock mode timings for csi, and table 37 describes the timing parameters (p1?p7) shown in the figures. a fram e starts with a rising/ falling edge on csi_vsync table 36. i.mx 6sololite supported ddr3/lpddr2 configurations parameter lpddr2 ddr3 clock frequency 400 mhz 400 mhz bus width 16-/32-bit 16-/32-bit channel single single chip selects 2 2
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 53 (vsync), then csi_hsync (hsync) is asserted and holds for th e entire line. the pixel clock, csi_pixclk (pixclk), is valid as long as hsync is asserted. figure 22. csi gated clock mode?sensor data at falling edge, latch data at rising edge figure 23. csi gated clock mode?sensor data at rising edge, latch data at falling edge table 37. csi gated clock mode timing parameters id parameter symbol min max units p1 csi_vsync to csi_hsync time tv2h 67.5 ns p2 csi_hsync setup time thsu 2 ns p3 csi data setup time tdsu 2.5 ns csi_pixclk csi_vsync csi_data[15:00] p5 p1 p3 p4 csi_hsync p2 p6 p7 csi_pixclk csi_vsync csi_data[15:00] p6 p1 p3 p4 csi_hsync p2 p5 p7
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 54 nxp semiconductors electrical characteristics 4.10.2.0.2 ungated clock mode timing figure 24 shows the ungated clock m ode timings of csi, and table 38 describes the timing parameters (p1?p6) that are shown in the figure. in ungated mode the csi_vsync and csi_pixclk signals are used, and the csi_hsync signal is ignored. figure 24. csi ungated clock mode?sensor data at falling edge, latch data at rising edge the csi enables the chip to connect directly to external cmos image sensors, which are classified as dumb or smart as follows: ? dumb sensors only support traditi onal sensor timing (vertical sync (vsync) and horizontal sync (hsync)) and output-only bayer and statistics data. ? smart sensors support ccir656 vi deo decoder formats and perform additional processing of the image (for example, image compression, image pr e-filtering, and various data output formats). p4 csi data hold time tdh 1.2 ns p5 csi pixel clock high time tclkh 7.5 ns p6 csi pixel clock low time tclkl 7.5 ns p7 csi pixel clock frequency fclk 66 mhz table 38. csi ungated clock mode timing parameters id parameter symbol min max units p1 csi_vsync to pixel clock time tvsync 67.5 ns p2 csi data setup time tdsu 2.5 ns p3 csi data hold time tdh 1.2 ns p4 csi pixel clock high time tclkh 7.5 ns p5 csi pixel clock low time tclkl 7.5 ns p6 csi pixel clock frequency fclk 66 mhz table 37. csi gated clock mode timing parameters (continued) id parameter symbol min max units csi_pixclk csi_vsync csi_data[15:00] p4 p1 p2 p3 p5 p6
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 55 the following subsections describe the cs i timing in gated and ungated clock modes. 4.10.3 ecspi timing parameters this section describes the timi ng parameters of the ecspi block. the ecspi has separate timing parameters for master and slave modes. 4.10.3.1 ecspi master mode timing figure 25 depicts the timing of ec spi in master mode and table 39 lists the ecspi master mode timing characteristics. figure 25. ecspi master mode timing diagram note ecspix_mosi is always driven (not tri-stated) between actual data transmissions. this limits the ecspi to be connected between a single master and a single slave. table 39. ecspi master mode timing parameters id parameter symbol min max unit cs1 ecspix_sclk cycle timeCread ?slow group 1 ? fast group 2 ecspix_sclk cycle timeCwrite t clk 46 40 15 ns cs2 ecspix_sclk high or low timeCread ?slow group 1 ? fast group 2 ecspix_sclk high or low timeCwrite t sw 22 20 7 ns cs3 ecspix_sclk rise or fall 3 t rise/fall n s cs4 ecspix_ssx pulse width t cslh half ecspix period ns cs5 ecspix_ssx lead time (cs setup time) t scs half ecspix_sclk period - 4 ns cs1 cs7 cs2 cs2 cs4 cs6 cs5 cs8 cs9 ecspix_sclk ecspix_ssx ecspix_mosi ecspix_miso ecspix_rdy cs10 cs3 cs3
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 56 nxp semiconductors electrical characteristics cs6 ecspix_ssx lag ti me (cs hold time) t hcs half ecspi_sclk period - 2 ns cs7 ecspix_mosi propagation delay (c load =20pf) t pdmosi -0.5 2 ns cs8 ecspix_miso setup time ?slow group 1 ? fast group 2 t smiso 14 12 ns cs9 ecspix_miso hold time t hmiso 0 n s cs10 ecspix_rdy to ecspix_ssx time 4 t sdry 5 n s 1 ecspi slow group includes: ecspi2/epdc_sdle, ecspi3/ epdc_d9, ecspi4/epdc_d1 2 ecspi fast group includes: ecspi1/lcd_data01, ecspi1/ecspi1_m iso, ecspi2/lcd_data10, ecspi 2/ecspi2_miso, ecspi3/audx_txc, ecspi3/sd2_dat1, ecspi4/key _row1, ecspi4/fec_rx_dv 3 see specific i/o ac parameters section 4.7, i/o ac parameters. 4 ecspix_rdy is sampled internally by ipg_clk and is asynchronous to all other ecspi signals. table 39. ecspi master mode timing parameters (continued) id parameter symbol min max unit
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 57 4.10.3.2 ecspi slave mode timing figure 26 depicts the timing of ec spi in slave mode and table 40 lists the ecspi slave mode timing characteristics. figure 26. ecspi slave mode timing diagram note ecspix_miso is always driven (not tri-stated) between actual data transmissions. this limits the ecspi to be connected between a single master and a single slave. table 40. ecspi slave mo de timing parameters id parameter symbol min max unit cs1 ecspix_sclk cycle timeCread ecspix_sclk cycle timeCwrite t clk 40 15 ns cs2 ecspix_sclk high or low timeCread ecspix_sclk high or low timeCwrite t sw 20 7 ns cs4 ecspix_ssx pulse width t cslh half sclk period ns cs5 ecspix_ssx lead time (cs setup time) t scs 5n s cs6 ecspix_ssx lag time (cs hold time) t hcs 5n s cs7 ecspix_mosi setup time t smosi 4n s cs8 ecspix_mosi hold time t hmosi 4n s cs9 ecspix_miso propagation delay (c load =20pf) t pdmiso 41 7n s cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 ecspix_sclk ecspix_ssx ecspix_miso ecspix_mosi
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 58 nxp semiconductors electrical characteristics 4.10.4 ultra high speed sd/sdio/ mmc host interface (usdhc) ac timing this section describes the electrical informat ion of the usdhc, which includes sd/emmc4.3 (single data rate) timing and emmc4.4/ 4.41 (dual date rate) timing. 4.10.4.1 sd/emmc4.3 (single data rate) ac timing parameters figure 27 depicts the timing of sd/emmc4.3, and table 41 lists the sd/emmc4.3 timing characteristics. figure 27. sd/emmc4.3 timing diagram table 41. sd/emmc4.3 interface timing parameters id parameter symbols min max unit card input clock 1 1 clock duty cycle will be in the range of 47% to 53%. sd1 clock frequency (low speed) f pp 2 2 in low speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 0 400 khz clock frequency (sd/sdio full speed/high speed) f pp 3 3 in normal (full) speed mode for sd/sdio ca rd, clock frequency can be any value between 0 C 25 mhz. in high-speed mode, clock frequency can be any value between 0 C 50 mhz. 0 25/50 mhz clock frequency (mmc full speed/high speed) f pp 4 4 in normal (full) speed mode for mmc card, clock frequency can be any value between 0 C 20 mhz. in high-speed mode, clock frequency can be any value between 0 C 52 mhz. 0 20/52 mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7ns sd3 clock high time t wh 7ns esdhc output/card inputs sdx_cmd, sdx_datax (reference to clk) sd6 esdhc output delay t od C6.6 3.6 ns esdhc input/card outputs sdx_cmd, sdx_datax (reference to clk) sd7 esdhc input setup time t isu 2.5 ns sd8 esdhc input hold time 5 t ih 1.5 ns sd1 sd3 sd5 sd4 sd7 sdx_clk sd2 sd8 sd6 output from usdhc to card input from card to usdhc sdx_data[7:0] sdx_data[7:0]
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 59 4.10.4.2 emmc4.4/4.41 (dual data rate) esdhcv3 ac timing parameters figure 28 depicts the timi ng of emmc4.4/4.41. table 42 lists the emmc4.4/4.41 ti ming characteristics. be aware that only sdx_datax is sampled on both e dges of the clock (not applicable to sdx_cmd). figure 28. emmc4.4/4. 41 timing diagram 5 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. table 42. emmc4.4/4.41 interface timing parameters id parameter symbols min max unit card input clock sd1 clock frequency (emmc4.4/4.41 ddr) f pp 052mhz sd1 clock frequency (sd3.0 ddr) f pp 050mhz usdhc output / card inputs sd_c md, sd_datax (reference to clk) sd2 usdhc output delay t od 2.5 7.1 ns usdhc input / card outputs sd_c md, sd_datax (reference to clk) sd3 usdhc input setup time t isu 1.7 ns sd4 usdhc input hold time t ih 1.5 ns sd1 sd3 output from esdhcv3 to card input from card to esdhcv3 sdx_data[7:0] sdx_clk sd4 sd2 sdx_data[7:0] sd2
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 60 nxp semiconductors electrical characteristics 4.10.4.3 sdr50/sdr104 ac timing parameters figure 29 depicts the timing of sdr50/sdr104, and table 43 lists the sdr50/sdr104 timing characteristics. figure 29. sdr50/sdr104 timing diagram table 43. sdr50/sdr104 interface timing parameters id parameter symbols min max unit card input clock sd1 clock frequency period t clk 4.8 ns sd2 clock low time t cl 0.46 t clk 0.54 t clk ns sd3 clock high time t ch 0.46 t clk 0.54 t clk ns usdhc output/card inputs sd_cmd, sd _datax in sdr50 (reference to clk) sd4 usdhc output delay t od C3 1 ns usdhc output/card inputs sd_cmd, sd_datax in sdr104 (reference to clk) sd5 usdhc output delay 1 1 if using key_col1, key_row1, key_col 2 and key_row2 for sd3_data4Csd3_ data7, note the difference in timing: t od minimum is -1.1 and t od maximum is 1.5. t od C1.6 0.74 ns usdhc input/card outputs sd_cmd, sd_datax in sdr50 (reference to clk) sd6 usdhc input setup time t isu 2.5 ns sd7 usdhc input hold time t ih 1.5 ns usdhc input/card outputs sd_cmd, sd_dat ax in sdr104 (reference to clk) 2 2 data window in sdr100 mode is variable. sd8 card output data window t odw 0.5 t clk n s
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 61 4.10.5 hs200 mode timing parameters figure 30 depicts the timing of hs200 mode, and table 44 lists the hs200 timing characteristics. figure 30. hs200 mode timing diagram 4.10.6 fec ac timing parameters this section describes the electrical information of the fast ethe rnet controller (f ec) module. the fec is designed to support both 10 and 100 mbps ethernet /ieee 802.3 networks. an external transceiver interface and transceiver function are required to co mplete the interface to the media. the fec supports the 10/100 mbps rmii (10 pins in total) and the 10 mbps (only 7-wire interface, which uses 7 of the rmii pins), for connection to an external ethernet transceive r. for the pin list of rmii and 7-wire, see the i.mx 6sololite reference manual. this section describes the ac timi ng specifications of the fec. the rmii signals are compatible with transceivers operating at a voltage of 3.3 v. table 44. hs200 interface timing parameters id parameter symbols min max unit card input clock sd1 clock frequency period t clk 5n s sd2 clock low time t cl 0.46 t clk 0.54 t clk ns sd3 clock high time t ch 0.46 t clk 0.54 t clk ns usdhc output/card inputs sd_cmd, sd x_datax in hs200 (reference to clk) sd5 usdhc output delay setup time t od -1.6 0.74 ns usdhc input/card outputs sd_cmd, sdx_d atax in hs200 (reference to clk) 1 1 hs200 is for 8 bits while sdr104 is for 4 bits. sd8 card output data window t odw 0.5 t clk n s 6&. elwrxwsxwiurpx6'+&wrh00& elwlqsxwiurph00&wrx6'+& 6' 6'6' 6' 6' 6' sd5
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 62 nxp semiconductors electrical characteristics 4.10.6.1 rmii mode timing parameters in rmii mode, fec_tx_clk is us ed as the ref_clk which is a 50 mhz 50 ppm continuous reference clock. fec_rx_dv is used as the crs_dv in rmii, and other signals under rmii mode include fec_tx_en, fec_tx_data[1:0], fec_rx _data[1:0] and optional fec_rx_er. the rmii mode timing parameters are shown in figure 31 and table 45 . figure 31. rmii mode signal timing diagram table 45. rmii signal timing parameters no. characteristics 1 1 test conditions: 25pf on each output signal. min max unit m16 ref_clk(fec_tx_clk) pulse width high 35% 65% ref_clk period m17 ref_clk(fec_tx_clk) pulse width low 35% 65% ref_clk period m18 ref_clk to fec_tx_data[1:0], fec_tx_en invalid 2 ns m19 ref_clk to fec_tx_data[1:0], fec_tx_en valid 16 ns m20 fec_rx_data[1:0], crs_dv(fec_rx_dv), fec_rx_er to ref_clk setup 4 ns m21 ref_clk to fec_rx_data[1:0], fec_rx_dv, fec_rx_er hold 2 ns ref_clk (input) fec_tx_en m16 m17 m18 m19 m20 m21 fec_rx_data[1:0] fec_tx_data[1:0] (output) fec_rx_er fec_rx_dv (input)
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 63 4.10.7 i 2 c module timing parameters this section describes the timing parameters of the i 2 c module. figure 32 depicts the timing of i 2 c module, and table 46 lists the i 2 c module timing characteristics. figure 32. i 2 c bus timing diagram table 46. i 2 c module timing parameters id parameter standard mode fast mode unit min max min max ic1 i2cx_scl cycle time 10 2.5 s ic2 hold time (repeated) start condition 4.0 0.6 s ic3 set-up time for stop condition 4.0 0.6 s ic4 data hold time 0 1 1 a device must internally provide a hold time of at least 300 ns for i2cx_sda signal in order to bridge the undefined region of the falling edge of i2cx_scl. 3.45 2 2 the maximum hold time has only to be met if the device does not stretch the low period (id no ic5) of the i2cx_scl signal. 0 1 0.9 2 s ic5 high period of i2cx_scl 4.0 0.6 s ic6 low period of the i2cx_scl 4.7 1.3 s ic7 set-up time for a repeated start condition 4.7 0.6 s ic8 data set-up time 250 100 3 3 a fast-mode i2c-bus device can be used in a standard-mode i2 c-bus system, but the requirement of set-up time (id no ic7) of 250 ns must be met. this automatically is the case if t he device does not stretch the low period of the i2cx_scl signal. if such a device does stretch the low period of the i2cx_scl si gnal, it must output the next data bit to the i2cx_sda line max_rise_time (ic9) + data_setup_time (ic7 ) = 1000 + 250 = 1250 ns (according to t he standard-mode i2c-bus specification) before the i2cx_scl line is released. ns ic9 bus free time between a stop and start condition 4.7 1.3 s ic10 rise time of both i2cx_sda and i2cx_scl signals 1000 20 + 0.1c b 4 4 c b = total capacitance of one bus line in pf. 300 ns ic11 fall time of both i2cx_sda and i2cx_scl signals 300 20 + 0.1c b 4 300 ns ic12 capacitive load for each bus line (c b ) 400 400 pf ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start i2cx_sda i2cx_scl ic1
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 64 nxp semiconductors electrical characteristics 4.10.8 pulse width modulator (pwm) timing parameters this section describes the electrical information of the pwm. the pwm can be programmed to select one of three clock signals as its source frequency. the selected clock signal is passed through a prescaler before being input to the counter. the out put is available at the pulse-w idth modulator output (pwmx_out) external pin (see external signals table in the i.mx 6sololite reference manua l for pwm pin assignments). figure 33 depicts the timing of the pwm, and table 47 lists the pwm timing parameters. figure 33. pwm timing diagram 4.10.9 scan jtag controller (sjc) timing parameters figure 34 depicts the sjc test clock input timing. figure 35 depicts the sjc boundary scan timing. figure 36 depicts the sjc test access port. signal parameters are listed in table 48 . figure 34. test clock input timing diagram table 47. pwm output timing parameters reference number parameter min max unit 1 system clk frequency 1 1 cl of pwmx_out = 30 pf 0 ipg_clk mhz 2a clock high time 12.29 ns 2b clock low time 9.91 ns system clock 2a 1 pwm output 3b 2b 3a 4b 4a jtag_tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 65 figure 35. boundary scan (jtag) timing diagram figure 36. test access port timing diagram jtag_tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6 jtag_tck (input) jtag_tdi (input) jtag_tdo (output) jtag_tdo (output) jtag_tdo (output) vih vil input data valid output data valid output data valid jtag_tms sj8 sj9 sj10 sj11 sj10
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 66 nxp semiconductors electrical characteristics figure 37. trst timing diagram 4.10.10 spdif timing parameters the sony/philips digital interconnect format (spdif) data is sent usi ng the bi-phase marking code. when encoding, the spdif data signal is modulated by a clock that is twice the bit ra te of the data signal. table 49 , figure 38 , and figure 39 show spdif timing parameters for the sony/philips digital interconnect format (spdif), including the timing of th e modulating rx clock (spdif_sr_clk) for spdif in rx mode and the timing of the modulating tx clock (spdif _st_clk) for spdif in tx mode. table 48. jtag timing parameters id parameter 1,2 all frequencies unit min max sj0 jtag_tck frequency of operation 1/(3?t dc ) 1 1 t dc = target frequency of sjc 0.001 22 mhz sj1 jtag_tck cycle time in crystal mode 45 ns sj2 jtag_tck clock pulse width measured at v m 2 2 v m = mid-point voltage 22.5 ns sj3 jtag_tck rise and fall times 3 ns sj4 boundary scan input data set-up time 5 ns sj5 boundary scan input data hold time 24 ns sj6 jtag_tck low to output data valid 40 ns sj7 jtag_tck low to output high impedance 40 ns sj8 jtag_tms, jtag_tdi data set-up time 5 ns sj9 jtag_tms, jtag_tdi data hold time 25 ns sj10 jtag_tck low to jtag_tdo data valid 44 ns sj11 jtag_tck low to jtag_tdo high impedance 44 ns sj12 jtag_trstb assert time 100 ns sj13 jtag_trstb set-up time to jtag_tck low 40 ns jtag_tck (input) jtag_trstb (input) sj13 sj12
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 67 figure 38. srck timing diagram figure 39. stclk timing diagram table 49. spdif timing parameters characteristics symbol timing parameter range unit min max spdif_in skew: asynchronous inputs, no specs apply 0.7 ns spdif_out output (load = 50pf) ?skew ? transition rising ? transition falling 1.5 24.2 31.3 ns spdif_out output (load = 30pf) ?skew ? transition rising ? transition falling 1.5 13.6 18.0 ns modulating rx clock (spdif_sr_clk) period srckp 40.0 ns spdif_sr_clk high period srckph 16.0 ns spdif_sr_clk low period srckpl 16.0 ns modulating tx clock (spdif_st_clk) period stclkp 40.0 ns spdif_st_clk high period stclkph 16.0 ns spdif_st_clk low pe riod stclkpl 16.0 ns spdif_sr_clk (output) v m v m srckp srckph srckpl spdif_st_clk (input) v m v m stclkp stclkph stclkpl
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 68 nxp semiconductors electrical characteristics 4.10.11 ssi timing parameters this section describes the timing parameters of the ssi module. the connectivity of the serial synchronous interfaces are summarized in table 50 . note the terms wl and bl used in the timi ng diagrams and tables refer to word length (wl) and bit length (bl). 4.10.11.1 ssi transmitter timing with internal clock figure 40 depicts the ssi transmitter internal clock timing and table 51 lists the timing parameters for the ssi transmitter internal clock. . figure 40. ssi transmitter internal clock timing diagram table 50. audmux port allocation port signal nomenclature type and access audmux port 1 ssi 1 internal audmux port 2 ssi 2 internal audmux port 3 aud3 external C aud3 i/o audmux port 4 aud4 external C i2c2 and lcd, or ecspi1, or sd2 i/o through iomuxc audmux port 5 aud5 external C epdc or sd3 i/o through iomuxc audmux port 6 aud6 external C fec or key_row and key_col through iomuxc audmux port 7 ssi 3 internal ss19 ss1 ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 note: audx_rxd input in synchronous mode only audx_txc (output) audx_txfs (wl) (output) audx_txfs (bl) (output) audx_rxd (input) audx_txd (output)
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 69 note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (txc/rxc = 0) and a non-i nverted frame sync (txfs/rxfs = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains va lid by inverting the clock signal txc/rxc and/or the fra me sync txfs/rxfs show n in the tables and in the figures. ? all timings are on audiomux pads when ssi is used for data transfer. ? the terms, wl and bl, refer to word length(wl) and bit length(bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of txd (for exampl e, during ac97 mode of operation). table 51. ssi transmitter timing with internal clock id parameter min max unit internal clock operation ss1 audx_txc/audx_rxc clock period 81.4 ns ss2 audx_txc/audx_rxc clock high period 36.0 ns ss4 audx_txc/audx_rxc clock low period 36.0 ns ss6 audx_txc high to audx_txfs (bl) high 15.0 ns ss8 audx_txc high to audx_txfs (bl) low 15.0 ns ss10 audx_txc high to audx_txfs (wl) high 15.0 ns ss12 audx_txc high to audx_txfs (wl) low 15.0 ns ss14 audx_txc/audx_rxc internal audx_txfs rise time 6.0 ns ss15 audx_txc/audx_rxc internal audx_txfs fall time 6.0 ns ss16 audx_txc high to audx_txd valid from high impedance 15.0 ns ss17 audx_txc high to audx_txd high/low 15.0 ns ss18 audx_txc high to audx_txd high impedance 15.0 ns synchronous internal clock operation ss42 audx_rxd setup before audx_txc falling 10.0 ns ss43 audx_rxd hold after audx_txc falling 0.0 ns
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 70 nxp semiconductors electrical characteristics 4.10.11.2 ssi receiver timing with internal clock figure 41 depicts the ssi receiver internal clock timing and table 52 lists the timing parameters for the receiver timing with the internal clock. figure 41. ssi receiver internal clock timing diagram table 52. ssi receiver with internal clock timing parameters id parameter min max unit internal clock operation ss1 audx_txc/audx_rxc clock period 81.4 ns ss2 audx_txc/audx_rxc clock high period 36.0 ns ss3 audx_txc/audx_rxc clock rise time 6.0 ns ss4 audx_txc/audx_rxc clock low period 36.0 ns ss5 audx_txc/audx_rxc clock fall time 6.0 ns ss7 audx_rxc high to audx_txfs (bl) high 15.0 ns ss9 audx_rxc high to audx_txfs (bl) low 15.0 ns ss11 audx_rxc high to audx_txfs (wl) high 15.0 ns ss13 audx_rxc high to audx_txfs (wl) low 15.0 ns ss20 audx_rxd setup time before audx_rxc low 10.0 ns ss21 audx_rxd hold time after audx_rxc low 0.0 ns ss50 ss48 ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 ss3 ss5 audx_txc (output) audx_txfs (bl) (output) audx_txfs (wl) (output) audx_rxd (input) audx_rxc (output)
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 71 note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (txc/rxc = 0) and a non-i nverted frame sync (txfs/rxfs = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains va lid by inverting the clock signal txc/rxc and/or the fra me sync txfs/rxfs show n in the tables and in the figures. ? all timings are on audiomux pads wh en ssi is being used for data transfer. ? the terms, wl and bl, refer to word length(wl) and bit length(bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of txd (for exampl e, during ac97 mode of operation). oversampling cl ock operation ss47 oversampling clock period 15.04 ns ss48 oversampling clock high period 6.0 ns ss49 oversampling clock rise time 3.0 ns ss50 oversampling clock low period 6.0 ns ss51 oversampling clock fall time 3.0 ns table 52. ssi receiver with internal clock timing parameters (continued) id parameter min max unit
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 72 nxp semiconductors electrical characteristics 4.10.11.3 ssi transmitter timing with external clock figure 42 depicts the ssi transmitte r external clock timing and table 53 lists the timing parameters for the transmitter timing wi th the external clock. figure 42. ssi transmitter exte rnal clock timing diagram table 53. ssi transmitter with external clock timing parameters id parameter min max unit external clock operation ss22 audx_txc/audx_rxc clock period 81.4 ns ss23 audx_txc/audx_rxc clock high period 36.0 ns ss24 audx_txc/audx_rxc clock rise time 6.0 ns ss25 audx_txc/audx_rxc clock low period 36.0 ns ss26 audx_txc/audx_rxc clock fall time 6.0 ns ss27 audx_txc high to audx_txfs (bl) high C10.0 15.0 ns ss29 audx_txc high to audx_txfs (bl) low 10.0 ns ss31 audx_txc high to audx_txfs (wl) high C10.0 15.0 ns ss33 audx_txc high to audx_txfs (wl) low 10.0 ns ss37 audx_txc high to audx_txd valid from high impedance 15.0 ns ss38 audx_txc high to audx_txd high/low 15.0 ns ss39 audx_txc high to audx_txd high impedance 15.0 ns ss45 ss33 ss24 ss26 ss25 ss23 note: audx_rxd input in synchronous mode only ss31 ss29 ss27 ss22 ss44 ss39 ss38 ss37 ss46 audx_txc (input) audx_txfs (bl) (input) audx_txfs (wl) (input) audx_txd (output) audx_rxd (input)
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 73 note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (txc/rxc = 0) and a non-i nverted frame sync (txfs/rxfs = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains va lid by inverting the clock signal txc/rxc and/or the fra me sync txfs/rxfs show n in the tables and in the figures. ? all timings are on audmux pads when ssi is used for data transfer. ? the terms wl and bl refer to wo rd length (wl) and bit length (bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of txd (for exampl e, during ac97 mode of operation). 4.10.11.4 ssi receiver timing with external clock figure 43 depicts the ssi receiver external clock timing and table 54 lists the timing parameters for the receiver timing with the external clock. figure 43. ssi receiver exte rnal clock timing diagram synchronous external clock operation ss44 audx_rxd setup before audx_txc falling 10.0 ns ss45 audx_rxd hold after audx_txc falling 2.0 ns ss46 audx_rxd rise/fall time 6.0 ns table 53. ssi transmitter with external clock timing parameters (continued) id parameter min max unit ss24 ss34 ss35 ss30 ss28 ss26 ss25 ss23 ss40 ss22 ss32 ss36 ss41 audx_txc (input) audx_txfs (bl) (input) audx_txfs (wl) (input) audx_rxd (input)
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 74 nxp semiconductors electrical characteristics note ? all the timings for the ssi are give n for a non-inverted serial clock polarity (txc/rxc=0) and a non-inverted frame sync (txfs/rxfs=0). if the polarity of th e clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal txc/rxc and/or the fra me sync txfs/rxfs show n in the tables and in the figures. ? all timings are on audmux pads wh en ssi is being used for data transfer. ? the terms, wl and bl, refer to word length(wl) and bit length(bl). ? for internal frame sync operation us ing external clock, the fs timing is same as that of txd (for exampl e, during ac97 mode of operation). table 54. ssi receiver timing with external clock id parameter min max unit external clock operation ss22 audx_txc/audx_rxc clock period 81.4 ns ss23 audx_txc/audx_rxc clock high period 36 ns ss24 audx_txc/audx_rxc clock rise time 6.0 ns ss25 audx_txc/audx_rxc clock low period 36 ns ss26 audx_txc/audx_rxc clock fall time 6.0 ns ss28 audx_rxc high to audx_txfs (bl) high C10 15.0 ns ss30 audx_rxc high to audx_txfs (bl) low 10 ns ss32 audx_rxc high to audx_txfs (wl) high C10 15.0 ns ss34 audx_rxc high to audx_txfs (wl) low 10 ns ss35 audx_txc/audx_rxc external audx_txfs rise time 6.0 ns ss36 audx_txc/audx_rxc external audx_txfs fall time 6.0 ns ss40 audx_rxd setup time before audx_rxc low 10 ns ss41 audx_rxd hold time after audx_rxc low 2 ns
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 75 4.10.12 uart i/o configurat ion and timing parameters 4.10.12.1 uart rs-232 i/o configuration in different modes the i.mx 6sololite uart interfaces can serve both as dte or dce device. this can be configured by the dcedte control bit (d efault 0 ? dce mode). table 55 shows the uart i/o configuration based on the enabled mode. 4.10.12.2 uart rs-232 serial mode timing the following sections describe the electrical information of the uart module in the rs-232 mode. 4.10.12.2.1 uart transmitter figure 44 depicts the transmit timing of uart in the rs-232 serial mode, with 8 data bit/1 stop bit format. table 56 lists the uart rs-232 serial mode transmit timing characteristics. figure 44. uart rs-232 serial mode transmit timing diagram table 55. uart i/o configuration vs. mode port dte mode dce mode direction description direction description uart_rts_b output rts from dte to dce input rts from dte to dce uart_cts_b input cts from dce to dte output cts from dce to dte uart_dtr_b output dtr from dte to dce input dtr from dte to dce uart_dsr_b input dsr from dce to dte output dsr from dce to dte uart_dcd_b input dcd from dce to dte output dcd from dce to dte uart_ri_b input ring from dce to dte output ring from dce to dte uart_tx_data input serial data from dce to dte output serial data from dce to dte uart_rx_data output serial data from dte to dce input serial data from dte to dce table 56. rs-232 serial mode transmit timing parameters id parameter symbol min max unit ua1 transmit bit time t tbit 1/f baud_rate 1 C t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk next start bit par bit ua1 ua1 ua1 ua1 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_ tx_data (output) bit 3 start bit stop bit possible parity bit
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 76 nxp semiconductors electrical characteristics 4.10.12.2.2 uart receiver figure 45 depicts the rs-232 serial m ode receive timing with 8 da ta bit/1 stop bit format. table 57 lists serial mode receive timing characteristics. figure 45. uart rs-232 serial mode receive timing diagram 4.10.12.2.3 uart irda mode timing the following subsections give the uart transmit and receive ti mings in irda mode. uart irda mode transmitter figure 46 depicts the uart irda mode transmit timing, with 8 data bit/1 stop bit format. table 58 lists the transmit timin g characteristics. figure 46. uart irda mode transmit timing diagram table 57. rs-232 serial mode receive timing parameters id parameter symbol min max unit ua2 receive bit time 1 1 the uart receiver can tolerate 1/(16 f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 f baud_rate ). t rbit 1/f baud_rate 2 C 1/(16 f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( frequency)/16. 1/f baud_rate + 1/(16 f baud_rate ) table 58. irda mode transmit timing parameters id parameter symbol min max unit ua3 transmit bit time in irda mode t tirbit 1/f baud_rate 1 C t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( frequency)/16. 2 t ref_clk : the period of uart reference clock ( after rfdiv divider). 1/f baud_rate + t ref_clk ua4 transmit ir pulse duration t tirpulse (3/16) (1/f baud_rate ) C t ref_clk (3/16) (1/f baud_rate ) + t ref_clk bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_ rx_data (input) bit 3 start bit stop bit next start bit possible parity bit par bit ua2 ua2 ua2 ua2 ua3 ua3 ua3 ua3 ua4 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_ tx_data (output) bit 3 start bit stop bit possible parity bit bit 6
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 77 uart irda mode receiver figure 47 depicts the uart irda mode receive ti ming, with 8 data bit/1 stop bit format. table 59 lists the receive timing characteristics. figure 47. uart irda mode receive timing diagram 4.10.13 usb hsic timing parameters this section describes the electrical information of the usb hsic port. note hsic is the ddr signal, the followi ng timing parameters are for both rising and falling edge. 4.10.13.1 transmit timing parameters figure 48. usb hsic transmit timing diagram table 59. irda mode receive timing parameters id parameter symbol min max unit ua5 receive bit time 1 in irda mode 1 the uart receiver can tolerate 1/(16 f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 f baud_rate ). t rirbit 1/f baud_rate 2 C 1/(16 f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( frequency)/16. 1/f baud_rate + 1/(16 f baud_rate ) ua6 receive ir pulse duration t rirpulse 1.41 s (5/16) (1/f baud_rate ) table 60. usb hsic transmit timing parameters name parameter min max unit comment tstrobe strobe period 4.166 4.167 ns todelay data output delay time 550 1350 ps measured at 50% point tslew strobe/data rising/falling time 0.7 2 v/ns averaged from 30% C 70% points uartx_rx_data (input) ua5 ua5 ua5 ua5 ua6 bit 7 stop bit possible parity bit bit 6 bit 1 bit 2 bit 0 bit 4 bit 5 bit 3 start bit usb_h_strobe usb_h_data todelay tstrobe todelay
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 78 nxp semiconductors electrical characteristics 4.10.13.2 receive timing parameters figure 49. usb hsic receive timing diagram 4.10.14 usb phy parameters this section describes the usb-otg phy and the usb host port phy parameters. the usb phy meets the electrical co mpliance requirements defined in the universal serial bus revi- sion 2.0 otg, usb host with the amendments below ( on-the-go and embedded host supplement to the usb revision 2.0 specification is not applicable to host port). ? usb engineering change notice ? title: 5v short circuit withstand requirement change ? applies to: universal serial bus specification, revision 2.0 ? errata for usb revision 2.0 april 27, 2000 as of 12/7/2000 ? usb engineering change notice ? title: pull-up/pull-down resistors ? applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice ? title: suspend current limit changes ? applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice ? title: usb 2.0 phase locked sofs ? applies to: universal serial bus specification, revision 2.0 ? on-the-go and embedded host supplement to the usb revision 2.0 specification ? revision 2.0 plus errata and ecn june 4, 2010 table 61. usb hsic receive timing parameters 1 1 the timings in the table are guaranteed when: ac i/o voltage is between 0.9x to 1x of the i/o supply ddr_sel configuration bits of the i/o are set to (10)b name parameter min max unit comment tstrobe strobe period 4.166 4.167 ns thold data hold time 300 ps measured at 50% point tsetup data setup time 365 ps measured at 50% point tslew strobe/data rising/falling time 0.7 2 v/ns averaged from 30% C 70% points usb_h_strobe usb_h_data thold tstrobe tsetup
electrical characteristics i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 79 ? battery charging specificati on (available from usb-if) ? revision 1.2, december 7, 2010 ? portable device only.
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 80 nxp semiconductors boot mode configuration 5 boot mode configuration this section provides information on boot mode configuration pins allo cation and boot devices interfaces allocation. 5.1 boot mode configuration pins table 62 provides boot options, functionalit y, fuse values, and associated pins. several input pins are also sampled at reset and can be used to override fuse values, depending on the va lue of bt_fuse_sel fuse. the boot option pins are in effect when bt_fuse_sel fuse is ?0? (cleared, which is the case for an unblown fuse). for detailed boot m ode options configured by the boot mode pins, s ee the i.mx 6sololite fuse map document and the system boot chap ter of the i.mx 6sol olite reference manual. table 62. fuses and associated pins used for boot ball name direction at reset efuse name boot mode selection boot_mode1 input boot mode selection boot_mode0 input boot mode selection boot options 1 lcd_dat0 input boot_cfg1[0] lcd_dat1 input boot_cfg1[1] lcd_dat2 input boot_cfg1[2] lcd_dat3 input boot_cfg1[3] lcd_dat4 input boot_cfg1[4] lcd_dat5 input boot_cfg1[5] lcd_dat6 input boot_cfg1[6] lcd_dat7 input boot_cfg1[7] lcd_dat8 input boot_cfg2[0] lcd_dat9 input boot_cfg2[1] lcd_dat10 input boot_cfg2[2] lcd_dat11 input boot_cfg2[3] lcd_dat12 input boot_cfg2[4] lcd_dat13 input boot_cfg2[5] lcd_dat14 input boot_cfg2[6] lcd_dat15 input boot_cfg2[7] lcd_dat16 input boot_cfg4[0] lcd_dat17 input boot_cfg4[1] lcd_dat18 input boot_cfg4[2]
boot mode configuration i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 81 5.2 boot devices interfaces allocation table 63 lists the interfaces that can be used by the boot process in accordance with the specific boot mode configuration. the table also describes the interface?s specif ic modes and iomuxc allocation, which are configured during boot when appropriate. lcd_dat19 input boot_cfg4[3] lcd_dat20 input boot_cfg4[4] lcd_dat21 input boot_cfg4[5] lcd_dat22 input boot_cfg4[6] lcd_dat23 input boot_cfg4[7] 1 pin value overrides fuse settings for bt_fuse_sel = 0. signal configuration as fuse override input at power up. these are special i/o lines that control the boot up configuration during product development. in production, the boot configuration can be controlled by fuses. table 63. interfaces allocation during boot interface ip instance allocated ball names during boot comment spi ecspi-1 ecspi1_miso, ec spi1_mosi, ecspi1_sclk, ecspi1_ss0, i2c1_scl , i2c1_sda, ecspi2_ss0 spi ecspi-2 ecspi2_miso, ec spi2_mosi, ecspi2_sclk, ecspi2_ss0, epdc_sdce0, epdc_gdclk, epdc_gdoe spi ecspi-3 epdc_d9, epdc_d8, epdc_d11, epdc_d10, epdc_d12, epdc_d13, epdc_d14 spi ecspi-4 epdc_d1, epdc_d0, epdc_d3, epdc_d2, epdc_d2, epdc_d5, epdc_d6 eim eim lcd_dat[21:6], key_ col[7:0], key_ row[7:0], epdc_d[15:8], epdc_vcom0, epdc_vcom1, epdc_bdr0, epdc_pwrct rl[2:0], epdc_sdce1 sd/mmc usdhc-1 refer to the table sd/mmc iomux pin configuration in the system boot chapter of the i.mx 6sololite applications processor reference manual 1, 4, or 8 bit fastboot sd/mmc usdhc-2 refer to the table sd/mmc iomux pin configuration in the system boot chapter of the i.mx 6sololite applications processor reference manual 1, 4, or 8 bit fastboot sd/mmc usdhc-3 refer to the table sd/mmc iomux pin configuration in the system boot chapter of the i.mx 6sololite applications processor reference manual 1, 4, or 8 bit fastboot (uhsi not supported) sd/mmc usdhc-4 refer to the table sd/mmc iomux pin configuration in the system boot chapter of the i.mx 6sololite applications processor reference manual 1, 4, or 8 bit fastboot i2c i2c-1 i2c1_scl, i2c1_sda table 62. fuses and associated pins used for boot (continued) ball name direction at reset efuse name
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 82 nxp semiconductors package information and contact assignments 6 package information and contact assignments this section includes the contact assignment information and mechanical package drawing. 6.1 updated signal naming convention the signal names of the i.mx6 series of products have been standardized to bett er align the signal names within the family and across the documentation. some of the benefits of thes e changes are as follows: ? the names are unique within the scope of an soc and within the series of products ? searches will return all occurrences of the named signal ? the names are consistent be tween i.mx 6 series products implementing the same modules ? the module instance is incorporated into the signal name this change applies only to signal na mes. the original ball names have been preserved to prevent the need to change schematics, bsdl m odels, ibis models, and so on. throughout this document, the updated signal names are used except where referenced as a ball name (such as the functional contact assignm ents table, ball map table, and so on). a master list of the signal name changes is in the document, imx 6 series signal name mapping (eb792). this list can be used to map the signal names used in older documentati on to the new standardized naming conventions. i2c i2c-2 i2c2_scl, i2c2_sda i2c i2c-3 aud_rxfs, aud_rxc usb usb_otg1_phy usb_otg1_dp usb_otg1_dn usb_otg1_vbus usb_otg1_chd_b usb_otg1_dp usb_otg1_dn usb_otg1_vbus table 63. interfaces allocation during boot (continued) interface ip instance allocated ball names during boot comment
package information and contact assignments i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 83 6.2 13 x 13mm package information 6.2.1 case 2240, 13 x 13 mm, 0. 5 mm pitch, 24 x 24 ball matrix figure 50 shows the top, bottom, and side views of the 1313 mm bga package. figure 50. 13 x 13, 0.5 mm bga package top, bottom, and side views
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 84 nxp semiconductors package information and contact assignments table 64 shows the 13 x 13 mm bga package details. table 64. 13 x 13, 0.5 mm bga package details parameter symbol common dimensions minimum normal maximum total thickness a 0.88 1.1 stand off a1 0.16 0.26 substrate thickness a2 0.26 ref mold thickness a3 0.54 ref body size d 13 bsc e1 3 b s c ball diameter 0.3 ball opening 0.275 ball width b 0.27 0.37 ball pitch e 0.5 bsc ball count n 432 edge ball center to center d1 11.5 bsc e1 11.5 bsc body center to contact ball sd 0.25 bsc se 0.25 bsc package edge tolerance aaa 0.1 mold flatness bbb 0.1 coplanarity ddd 0.08 ball offset (package) eee 0.15 ball offset (ball) fff 0.05
package information and contact assignments i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 85 6.2.2 13 x 13 mm ground, power, sens e, not connected, and reference contact assignments table 65 shows the device connection list for ground, power, sense, and reference contact signals. table 65. 13 x 13 mm supplies contact assignment supply rail name ball (s) position(s) remark dram_vref n5 gnd a1, a4, a7, a24, c6, c10, c 14, c19, d1, d2, e5, g1, g8, g9, g10, g11, g13, g14, g15, g17, g18, h3, h7, h18, h22, j5, k1, l7, l9, l10, l11, l12, l13, l14, l15, l16, m5, m7, m8, m9, m10, m11, m12, m13, m14, m 15, m16, m17, n3, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n22, p9, p10, p11, p12, p13, p14, p15, p16, r1, t5, u3, u7, u18, u22, v1, v8, v9, v10, v11, v12, v13, v14, v15, v16, v18, y5, aa1, aa2, ab10, ab14, ab18, ac18, ad1, ad4, ad7, ad24 gnd_kelvin v17 must be connected gpanaio ad22 analog output for nxp use only. this output must remain unconnected. nvcc_1p2v w7 nvcc18_io e14, e15, m20, y11 nvcc33_io h10, h11, h14, h15, l18, m18, t19, u10, u11 nvcc_dram e6, y6, g7, h6, j6, n6, p7, t6 , u6, v7 supply of the ddr interface nvcc_dram_2p5 m6 nvcc_pll y19 vdd_arm_cap j15, j16, j17, j18, k15, k16, k17, k18 secondary supply for the arm0 and arm1 cores (internal regulator outputrequires capa citor if internal regulator is used) vdd_arm_in j12, j13, j14, k12, k13, k14 primary supply, for the arm0 and arm1 core regulator vdd_high_cap r14, r15, t14, t15 secondary supply for the 2.5 v domain (internal regulator outputrequires capa citor if internal regulator is used) vdd_high_in r12, r13, t12, t13 primary supply for the 2.5 v regulator vdd_pu_cap r7, r8, r9, t7, t8, t9 secondary supply for the vpu and gpus (internal regulator outputrequires capa citor if internal regulator is used) vdd_pu_in r10, r11, t10, t11 vdd_snvs_cap ad20 secondary supply for the snvs (internal regulator outputrequires capacitor if internal regulator is used)
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 86 nxp semiconductors package information and contact assignments table 66 displays an alpha-sorted list of the signal assignments including power rails. the table also includes out of reset pad state. vdd_snvs_in ac20 primary supply, for the snvs regulator vdd_soc_cap j7, j8, j9, k7, k8, k9, n18, p18, r18 secondary supply for the soc and pu (internal regulator outputrequires capacitor if internal regulator is used) vdd_soc_in j10, j11, k10, k11, r16, r17, t16, t17, t18 primary supply, for the soc and pu regulators vdd_usb_cap u14 secondary supply for the 3v domain (usbphy, mlpbphy, efuse), internal regulator output, requires capacitor if internal regulator is used. usb_otg1_vbus aa18 usb_otg2_vbus ad18 zqpad h2 connect zqpad to an external 240 ohm 1% resistor to gnd. this is a reference used during dram output buffer driver calibration. nc c4, c5, c8, c9, c12, c13, c16, c17, c20, c21, d4, d5, d8, d9, d12, d13, d16, d17, d20, d21, e8, e9, e1 2, e13, e16, e17, f3, f4, f5, f6, f8, f9, f12, f13, f16, f17, f19, f20, f21, f22, g3, g4, g5, g6, g19, g20, g21, g22, h8, h9, h12, h13, h16, h17, k3, k4, k5, k6, k19, k20, k21, k22, l3, l4, l5, l6, l8, l17, l19, l20, l21, l22, p3, p4, p5, p6, p8, p17, p19, p20, p21, p22, r3, r4, r5, r6, r19, r20, r21, r22, u8, u9, u12, u13, u16, u17, v3, v4, v5, v6, v19, v20, v21, v22, w3, w4, w5, w6, w8, w9, w12, w13, w16, w17, w19, w20, w21, w22, y8, y9, y12, y13, y16, y17, aa4, aa5, aa8, aa9, aa12, aa13, aa16, aa17, aa20, aa2 1, ab4, ab5, ab8, ab9, ab12, ab13, ab16, ab17 ab20, ab21 no connections. table 66. 13 x 13 mm functional contact assignments ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3 aud_mclk h19 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[6] input keeper aud_rxc j21 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[1] input keeper aud_rxd j20 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[2] input keeper table 65. 13 x 13 mm supplies contact assignment (continued) supply rail name ball (s) position(s) remark
package information and contact assignments i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 87 aud_rxfs j19 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[0] input keeper aud_txc h20 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[3] input keeper aud_txd j22 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[5] input keeper aud_txfs h21 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[4] input keeper boot_mode0 ac15 vdd_snvs_in gpio alt0 src_boot_mode0 input keeper boot_mode1 ab15 vdd_snvs_in gpio alt0 src_boot_mode1 input keeper clk1_n ad23 vddhigh_cap clk1_n clk1_p ac23 vddhigh_cap clk1_p dram_a0 u4 nvcc_dram ddr alt0 dram_addr00 output 0 dram_a1 u5 nvcc_dram ddr alt0 dram_addr01 output 0 dram_a10 j2 nvcc_dram ddr alt0 dram_addr10 output 0 dram_a11 t2 nvcc_dram ddr alt0 dram_addr11 output 0 dram_a12 u2 nvcc_dram ddr alt0 dram_addr12 output 0 dram_a13 h5 nvcc_dram ddr alt0 dram_addr13 output 0 dram_a14 r2 nvcc_dram ddr alt0 dram_addr14 output 0 dram_a15 k2 nvcc_dram ddr alt0 dram_addr15 output 0 dram_a2 t3 nvcc_dram ddr alt0 dram_addr02 output 0 dram_a3 t4 nvcc_dram ddr alt0 dram_addr03 output 0 dram_a4 n4 nvcc_dram ddr alt0 dram_addr04 output 0 dram_a5 m3 nvcc_dram ddr alt0 dram_addr05 output 0 dram_a6 m4 nvcc_dram ddr alt0 dram_addr06 output 0 dram_a7 h4 nvcc_dram ddr alt0 dram_addr07 output 0 dram_a8 j3 nvcc_dram ddr alt0 dram_addr08 output 0 dram_a9 j4 nvcc_dram ddr alt0 dram_addr09 output 0 dram_cas_b p1 nvcc_dram ddr alt0 dram_cas_b output 0 dram_cs0_b n2 nvcc_dram ddr alt0 dram_cs0_b output 0 dram_cs1_b l2 nvcc_dram ddr alt0 dram_cs1_b output 0 dram_d0 ac2 nvcc_dram ddr alt0 dram_data00 input pu (100k) dram_d1 ac1 nvcc_dram ddr alt0 dram_data01 input pu (100k) dram_d10 e3 nvcc_dram ddr alt0 dram_data10 input pu (100k) dram_d11 d3 nvcc_dram ddr alt0 dram_data11 input pu (100k) dram_d12 c1 nvcc_dram ddr alt0 dram_data12 input pu (100k) dram_d13 c2 nvcc_dram ddr alt0 dram_data13 input pu (100k) dram_d14 b1 nvcc_dram ddr alt0 dram_data14 input pu (100k) dram_d15 b2 nvcc_dram ddr alt0 dram_data15 input pu (100k) dram_d16 ad8 nvcc_dram ddr alt0 dram_data16 input pu (100k) table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 88 nxp semiconductors package information and contact assignments dram_d17 ac7 nvcc_dram ddr alt0 dram_data17 input pu (100k) dram_d18 ad6 nvcc_dram ddr alt0 dram_data18 input pu (100k) dram_d19 ac6 nvcc_dram ddr alt0 dram_data19 input pu (100k) dram_d2 ab2 nvcc_dram ddr alt0 dram_data02 input pu (100k) dram_d20 ad5 nvcc_dram ddr alt0 dram_data20 input pu (100k) dram_d21 ac5 nvcc_dram ddr alt0 dram_data21 input pu (100k) dram_d22 ac4 nvcc_dram ddr alt0 dram_data22 input pu (100k) dram_d23 ad3 nvcc_dram ddr alt0 dram_data23 input pu (100k) dram_d24 a3 nvcc_dram ddr alt0 dram_data24 input pu (100k) dram_d25 b4 nvcc_dram ddr alt0 dram_data25 input pu (100k) dram_d26 b5 nvcc_dram ddr alt0 dram_data26 input pu (100k) dram_d27 a5 nvcc_dram ddr alt0 dram_data27 input pu (100k) dram_d28 b6 nvcc_dram ddr alt0 dram_data28 input pu (100k) dram_d29 a6 nvcc_dram ddr alt0 dram_data29 input pu (100k) dram_d3 ab1 nvcc_dram ddr alt0 dram_data03 input pu (100k) dram_d30 b7 nvcc_dram ddr alt0 dram_data30 input pu (100k) dram_d31 a8 nvcc_dram ddr alt0 dram_data31 input pu (100k) dram_d4 aa3 nvcc_dram ddr alt0 dram_data04 input pu (100k) dram_d5 y3 nvcc_dram ddr alt0 dram_data05 input pu (100k) dram_d6 y1 nvcc_dram ddr alt0 dram_data06 input pu (100k) dram_d7 y2 nvcc_dram ddr alt0 dram_data07 input pu (100k) dram_d8 e2 nvcc_dram ddr alt0 dram_data08 input pu (100k) dram_d9 e1 nvcc_dram ddr alt0 dram_data09 input pu (100k) dram_dqm0 v2 nvcc_dram ddr alt0 dram_dqm0 output 0 dram_dqm1 g2 nvcc_dram ddr alt0 dram_dqm1 output 0 dram_dqm2 ab3 nvcc_dram ddr alt0 dram_dqm2 output 0 dram_dqm3 c3 nvcc_dram ddr alt0 dram_dqm3 output 0 dram_ras_b n1 nvcc_dram ddr alt0 dram_ras_b output 0 dram_reset_b d6 nvcc_dram ddr alt0 dram_reset_b output 0 dram_sdba0 j1 nvcc_dram ddr alt0 dram_sdba0 output 0 dram_sdba1 t1 nvcc_dram ddr alt0 dram_sdba1 output 0 dram_sdba2 h1 nvcc_dram ddr alt0 dram_sdba2 output 0 dram_sdcke0 p2 nvcc_dram ddr alt0 dram_sdcke0 output 0 dram_sdcke1 m2 nvcc_dram ddr alt0 dram_sdcke1 output 0 dram_sdclk_0 l1 nvcc_dram ddrclk alt0 dram_sdclk0_p output 0 dram_sdclk_0_b m1 nvcc_dram ddrclk dram_sdclk0_n dram_sdodt0 y4 nvcc_dram ddr alt0 dram_odt0 output 0 dram_sdodt1 e4 nvcc_dram ddr alt0 dram_odt1 output 0 dram_sdqs0 w2 nvcc_dram ddrclk alt0 dram_sdqs0_p input hi-z table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
package information and contact assignments i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 89 dram_sdqs0_b w1 nvcc_dram ddrclk dram_sdqs0_n dram_sdqs1 f1 nvcc_dram ddrclk alt0 dram_sdqs1_p input hi-z dram_sdqs1_b f2 nvcc_dram ddrclk dram_sdqs1_n dram_sdqs2 ac3 nvcc_dram ddrclk alt0 dram_sdqs2_p input hi-z dram_sdqs2_b ad2 nvcc_dram ddrclk dram_sdqs2_n dram_sdqs3 b3 nvcc_dram ddrclk alt0 dram_sdqs3_p input hi-z dram_sdqs3_b a2 nvcc_dram ddrclk dram_sdqs3_n dram_sdwe u1 nvcc_dram ddr alt0 dram_sdwe output 0 ecspi1_miso m19 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[10] input keeper ecspi1_mosi n20 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[9] input keeper ecspi1_sclk n19 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[8] input keeper ecspi1_ss0 m21 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[11] input keeper ecspi2_miso t20 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[14] input keeper ecspi2_mosi u20 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[13] input keeper ecspi2_sclk u19 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[12] input keeper ecspi2_ss0 t21 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[15] input keeper epdc_bdr0 c18 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[5] input keeper epdc_bdr1 b18 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[6] input keeper epdc_d0 a18 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[7] input keeper epdc_d1 a17 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[8] input keeper epdc_d10 g16 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[17] input keeper epdc_d11 f14 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[18] input keeper epdc_d12 d14 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[19] input keeper epdc_d13 b14 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[20] input keeper epdc_d14 a14 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[21] input keeper table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 90 nxp semiconductors package information and contact assignments epdc_d15 a13 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[22] input keeper epdc_d2 b17 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[9] input keeper epdc_d3 a16 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[10] input keeper epdc_d4 b16 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[11] input keeper epdc_d5 a15 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[12] input keeper epdc_d6 b15 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[13] input keeper epdc_d7 c15 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[14] input keeper epdc_d8 d15 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[15] input keeper epdc_d9 f15 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[16] input keeper epdc_gdclk a12 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[31] input keeper epdc_gdoe b13 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[0] input keeper epdc_gdrl b12 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[1] input keeper epdc_gdsp a11 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[2] input keeper epdc_pwrcom b11 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[11] input keeper epdc_pwrctrl0 d11 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[7] input keeper epdc_pwrctrl1 e11 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[8] input keeper epdc_pwrctrl2 f11 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[9] input keeper epdc_pwrctrl3 g12 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[10] input keeper epdc_pwrint f10 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[12] input keeper epdc_pwrstat e10 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[13] input keeper epdc_pwrwakeu p d10 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[14] input keeper epdc_sdce0 c11 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[27] input keeper table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
package information and contact assignments i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 91 epdc_sdce1 a10 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[28] input keeper epdc_sdce2 b9 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[29] input keeper epdc_sdce3 a9 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[30] input keeper epdc_sdclk b10 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[23] input keeper epdc_sdle b8 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[24] input keeper epdc_sdoe e7 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[25] input keeper epdc_sdshr f7 nvcc33_io nvcc18_io gpio alt5 gpio1_gpio[26] input keeper epdc_vcom0 c7 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[3] input keeper epdc_vcom1 d7 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[4] input keeper fec_crs_dv ac9 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[25] input keeper fec_mdc aa7 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[23] input keeper fec_mdio ab7 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[20] input keeper fec_ref_clk w10 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[26] input keeper fec_rx_er ad9 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[19] input keeper fec_rxd0 aa10 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[17] input keeper fec_rxd1 ac10 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[18] input keeper fec_tx_clk ac8 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[21] input keeper fec_tx_en ad10 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[22] input keeper fec_txd0 y10 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[24] input keeper fec_txd1 w11 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[16] input keeper hsic_dat aa6 nvcc_1p2v ddr usb_h_data input pd (100k) hsic_strobe ab6 nvcc_1p25 ddr usb_h_strobe input pd (100k) table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 92 nxp semiconductors package information and contact assignments i2c1_scl ac13 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[12] input keeper i2c1_sda ad13 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[13] input keeper i2c2_scl e18 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[14] input keeper i2c2_sda d18 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[15] input keeper jtag_mod y14 nvcc33_io gpio alt5 jtag_mode pu (100k) jtag_tck aa14 nvcc33_io gpio alt5 jtag_tck pu (47k) jtag_tdi w14 nvcc33_io gpio alt5 jtag_tdi pu (47k) jtag_tdo w15 nvcc33_io gpio alt5 jtag_tdo keeper jtag_tms y15 nvcc33_io gpio alt5 jtag_tms pu (47k) jtag_trstb aa15 nvcc33_io gpio alt5 jtag_trstb pu (47k) key_col0 g23 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[24] input keeper key_col1 f23 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[26] input keeper key_col2 e23 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[28] input keeper key_col3 e22 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[30] input keeper key_col4 e20 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[0] input keeper key_col5 d24 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[2] input keeper key_col6 d22 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[4] input keeper key_col7 c23 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[6] input keeper key_row0 g24 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[25] input keeper key_row1 f24 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[27] input keeper key_row2 e24 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[29] input keeper key_row3 e21 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[31] input keeper key_row4 e19 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[1] input keeper key_row5 d23 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[3] input keeper table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
package information and contact assignments i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 93 key_row6 c24 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[5] input keeper key_row7 b24 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[7] input keeper lcd_clk t22 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[15] input keeper lcd_dat0 y24 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[20] input keeper lcd_dat1 w23 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[21] input keeper lcd_dat10 r23 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[30] input keeper lcd_dat11 r24 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[31] input keeper lcd_dat12 p23 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[0] input keeper lcd_dat13 p24 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[1] input keeper lcd_dat14 n21 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[2] input keeper lcd_dat15 n23 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[3] input keeper lcd_dat16 n24 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[4] input keeper lcd_dat17 m22 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[5] input keeper lcd_dat18 m23 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[6] input keeper lcd_dat19 m24 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[7] input keeper lcd_dat2 w24 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[22] input keeper lcd_dat20 l23 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[8] input keeper lcd_dat21 l24 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[9] input keeper lcd_dat22 k23 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[10] input keeper lcd_dat23 k24 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[11] input keeper lcd_dat3 v23 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[23] input keeper lcd_dat4 v24 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[24] input keeper table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 94 nxp semiconductors package information and contact assignments lcd_dat5 u21 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[25] input keeper lcd_dat6 u23 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[26] input keeper lcd_dat7 u24 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[27] input keeper lcd_dat8 t23 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[28] input keeper lcd_dat9 t24 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[29] input keeper lcd_enable j24 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[16] input keeper lcd_hsync h23 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[17] input keeper lcd_reset h24 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[19] input keeper lcd_vsync j23 nvcc33_io nvcc18_io gpio alt5 gpio2_gpio[18] input keeper onoff w18 vdd_snvs_in gpio src_onoff input pu (100k) pmic_on_req ad15 vdd_snvs_in gpio alt0 snvs_pmic_on_req output open drain with pu (100k) pmic_stby_req ad16 vdd_snvs_in gp io alt0 ccm_pmic_stby_req output 0 por_b ac16 vdd_snvs_in gpio alt0 src_por_b input pu (100k) pwm1 y7 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[23] input keeper ref_clk_24m ac14 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[21] input keeper ref_clk_32k ad14 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[22] input keeper rtc_xtali ab19 vdd_snvs_cap rtc_xtali rtc_xtalo aa19 vdd_snvs_cap rtc_xtalo sd1_clk b20 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[15] input keeper sd1_cmd b21 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[14] input keeper sd1_dat0 b23 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[11] input keeper sd1_dat1 a23 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[8] input keeper sd1_dat2 c22 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[13] input keeper table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
package information and contact assignments i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 95 sd1_dat3 b22 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[6] input keeper sd1_dat4 a22 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[12] input keeper sd1_dat5 a21 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[9] input keeper sd1_dat6 a20 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[7] input keeper sd1_dat7 a19 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[10] input keeper sd2_clk ac24 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[5] input keeper sd2_cmd ab24 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[4] input keeper sd2_dat0 ab22 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[1] input keeper sd2_dat1 ab23 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[30] input keeper sd2_dat2 aa22 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[3] input keeper sd2_dat3 aa23 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[28] input keeper sd2_dat4 aa24 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[2] input keeper sd2_dat5 y20 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[31] input keeper sd2_dat6 y21 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[29] input keeper sd2_dat7 y22 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[0] input keeper sd2_rst y23 nvcc33_io nvcc18_io gpio alt5 gpio4_gpio[27] input keeper sd3_clk ab11 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[18] input keeper sd3_cmd aa11 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[21] input keeper sd3_dat0 ac11 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[19] input keeper sd3_dat1 ad11 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[20] input keeper sd3_dat2 ac12 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[16] input keeper sd3_dat3 ad12 nvcc33_io nvcc18_io gpio alt5 gpio5_gpio[17] input keeper table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 96 nxp semiconductors package information and contact assignments for most of the signals, the state during reset is same as the state after reset, given in the out of reset condition column of table 66 . however, there are some signals for wh ich the state during reset is different from the state after reset. these signals al ong with their state durin g reset are given in table 67 . tamper y18 vdd_snvs_in gpio alt0 snvs_tamper input test_mode u15 vdd_snvs_in gpio alt0 test_mode input uart1_rxd b19 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[16] input keeper uart1_txd d19 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[17] input keeper usb_otg_chd_b ac22 vdd_usb_cap analog usb_otg_chd_b usb_otg1_dn ad19 vdd_usb_cap analog usb_otg1_dn usb_otg1_dp ac19 vdd_usb_cap analog usb_otg1_dp usb_otg2_dn ad17 vdd_usb_cap analog usb_otg2_dn usb_otg2_dp ac17 vdd_usb_cap analog usb_otg2_dp wdog_b f18 nvcc33_io nvcc18_io gpio alt5 gpio3_gpio[18] input keeper xtali ad21 nvcc_pll analog xtali xtalo ac21 nvcc_pll analog xtalo zqpad h2 nvcc_dram zqpad dram_zqpad input hi-z 1 all balls marked power group nvcc33_io or nvcc18_io are dual-voltage ios. the user supplies nvcc33_io and nvcc18_io. in the iomux for each ball, the user selects either 3.3 v or 1.8 v operation using the lve field in the pad control register for each ball. 2 the state immediately after reset and before rom firmware or software has executed. 3 variance of the pull-up and pull-down strengt hs are shown in the tables as follows: ? table 21, "dvgpio i/o dc parameters," on page 33 ? table 22, "lpddr2 i/o dc electrical parameters," on page 34 ? table 23, "ddr3 i/o dc electrical parameters," on page 34 table 67. signals with differing before reset and after reset states ball name before reset state input/output value eim_a16 input pd (100k) eim_a17 input pd (100k) eim_a18 input pd (100k) eim_a19 input pd (100k) eim_a20 input pd (100k) eim_a21 input pd (100k) table 66. 13 x 13 mm functional contact assignments (continued) ball name ball power group 1 ball type out of reset condition 2 default mode (reset mode) default function input/output value 3
package information and contact assignments i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 97 eim_a22 input pd (100k) eim_a23 input pd (100k) eim_a24 input pd (100k) eim_eb0 input pd (100k) eim_eb1 input pd (100k) eim_lba input pd (100k) eim_rw input pd (100k) eim_gpio19 input pd (100k) eim_gpio17 input pd (100k) key_col0 input pd (100k) table 67. signals with differing before reset and after reset states (continued) ball name before reset state input/output value
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 98 nxp semiconductors package information and contact assignments 6.2.3 13 x 13 mm, 0.5 mm pitch ball map table 68 shows the mapbga 13 x 13 mm, 0.5 mm pitch ball map. table 68. 13 x 13 mm, 0.5 mm pitch ball map a b c d e f g h j k l m n p r t u v w y aa ab ac ad 24 gnd key_row7 key_row6 key_col5 key_row2 key_row1 key_row0 lcd_reset lcd_enable lcd_dat23 lcd_dat21 lcd_dat19 lcd_dat16 lcd_dat13 lcd_dat11 lcd_dat9 lcd_dat7 lcd_dat4 lcd_dat2 lcd_dat0 sd2_dat4 sd2_cmd sd2_clk gnd 23 sd1_dat1 sd1_dat0 key_col7 key_row5 key_col2 key_col1 key_col0 lcd_hsync lcd_vsync lcd_dat22 lcd_dat20 lcd_dat18 lcd_dat15 lcd_dat12 lcd_dat10 lcd_dat8 lcd_dat6 lcd_dat3 lcd_dat1 sd2_rst sd2_dat3 sd2_dat1 clk1_p clk1_n 22 sd1_dat4 sd1_dat3 sd1_dat2 key_col6 key_col3 nc nc gnd aud_txd nc nc lcd_dat17 gnd nc nc lcd_clk gnd nc nc sd2_dat7 sd2_dat2 sd2_dat0 usb_otg_chd_b gpanaio 21 sd1_dat5 sd1_cmd nc nc key_row3 nc nc aud_txfs aud_rxc nc nc ecspi1_ss0 lcd_dat14 nc nc ecspi_ss0 lcd_dat5 nc nc sd2_dat6 nc nc xtalo xtali 20 sd1_dat6 sd1_clk nc nc key_col4 nc nc aud_txc aud_rxd nc nc nvcc18_io ecspi1_mosi nc nc ecspi2_miso ecspi2_mosi nc nc sd2_dat5 nc nc vdd_snvs_in vdd_snvs_cap 19 sd1_dat7 uart1_rxd gnd uart1_txd key_row4 nc nc aud_mclk aud_rxfs nc nc ecspi1_miso ecspi1_sclk nc nc nvcc33_io ecspi2_sclk nc nc nvcc_pll rtc_xtalo rtc_xtali usb_otg1_dp usb_otg1_dn 18 epdc_d0 epdc_bdr1 epdc_bdr0 i2c2_sda i2c2_scl wdog_b gnd gnd vdd_arm_cap vdd_arm_cap nvcc33_io nvcc33_io vdd_soc_cap vdd_soc_cap vdd_soc_cap vdd_soc_in gnd gnd onoff tamper usb_otg1_vbus gnd gnd usb_otg2_vbus 17 epdc_d1 epdc_d2 nc nc nc nc gnd nc vdd_arm_cap vdd_arm_cap nc gnd gnd nc vdd_soc_in vdd_soc_in nc gnd_kelvin nc nc nc nc usb_otg2_dp usb_otg2_dn
package information and contact assignments i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 99 16 epdc_d3 epdc_d4 nc nc nc nc epdc_d10 nc vdd_arm_cap vdd_arm_cap gnd gnd gnd gnd vdd_soc_in vdd_soc_in nc gnd nc nc nc nc por_b pmic_stby_req 15 epdc_d5 epdc_d6 epdc_d7 epdc_d8 nvcc18_io epdc_d9 gnd nvcc33_io vdd_arm_cap vdd_arm_cap gnd gnd gnd gnd vdd_high_cap vdd_high_cap test_mode gnd jtag_tdo jtag_tms jtag_trstb boot_mode1 boot_mode0 pmic_on_req 14 epdc_d14 epdc_d13 gnd epdc_d12 nvcc18_io epdc_d11 gnd nvcc33_io vdd_arm_in vdd_arm_in gnd gnd gnd gnd vdd_high_cap vdd_high_cap vdd_usb_cap gnd jtag_tdi jtag_mod jtag_tck gnd ref_clk_24m ref_clk_32k 13 epdc_d15 epdc_gdoe nc nc nc nc gnd nc vdd_arm_in vdd_arm_in gnd gnd gnd gnd vdd_high_in vdd_high_in nc gnd nc nc nc nc i2c1_scl i2c1_sda 12 epdc_gdclk epdc_gdrl nc nc nc nc epdc_pwrctrl3 nc vdd_arm_in vdd_arm_in gnd gnd gnd gnd vdd_high_in vdd_high_in nc gnd nc nc nc nc sd3_dat2 sd3_dat3 11 epdc_gdsp epdc_prwcom epdc_sdce0 epdc_pwrctrl0 epdc_pwrctrl1 epdc_pwrctrl2 gnd nvcc33_io vdd_soc_in vdd_soc_in gnd gnd gnd gnd vdd_pu_in vdd_pu_in nvcc33_io gnd fec_txd1 nvcc18_io sd3_cmd sd3_clk sd3_dat0 sd3_dat1 10 epdc_sdce1 epdc_sdclk gnd epdc_pwrwakeup epdc_pwrstat epdc_pwrint gnd nvcc33_io vdd_soc_in vdd_soc_in gnd gnd gnd gnd vdd_pu_in vdd_pu_in nvcc33_io gnd fec_ref_clk fec_txd0 fec_rxd0 gnd fec_rxd1 fec_tx_en 9 epdc_sdce3 epdc_sdce2 nc nc nc nc gnd nc vdd_soc_cap vdd_soc_cap gnd gnd gnd gnd vdd_pu_cap vdd_pu_cap nc gnd nc nc nc nc fec_crs_dv fec_rx_er table 68. 13 x 13 mm, 0.5 mm pitch ball map (continued) a b c d e f g h j k l m n p r t u v w y aa ab ac ad
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 100 nxp semiconductors package information and contact assignments 8 dram_d31 epdc_sdle nc nc nc nc gnd nc vdd_soc_cap vdd_soc_cap nc gnd gnd nc vdd_pu_cap vdd_pu_cap nc gnd nc nc nc nc fec_tx_clk dram_d16 7 gnd dram_d30 epdc_vcom0 epdc_vcom1 epdc_sdoe epdc_sdshr nvcc_dram gnd vdd_soc_cap vdd_soc_cap gnd gnd gnd nvcc_dram vdd_pu_cap vdd_pu_cap gnd nvcc_dram nvcc_1p2 pwm1 fec_mdc fec_mdio dram_d17 gnd 6 dram_d29 dram_d28 gnd dram_reset nvcc_dram nc nc nvcc_dram nvcc_dram nc nc nvcc_dram_2p5 nvcc_dram nc nc nvcc_dram nvcc_dram nc nc nvcc_dram hsic_dat hsic_strobe dram_d19 dram_d18 5 dram_d27 dram_d26 nc nc gnd nc nc dram_a13 gnd nc nc gnd dram_vref nc nc gnd dram_a1 nc nc gnd nc nc dram_d21 dram_d20 4 gnd dram_d25 nc nc dram_sdodt1 nc nc dram_a7 dram_a9 nc nc dram_a6 dram_a4 nc nc dram_a3 dram_a0 nc nc dram_sdodt0 nc nc dram_d22 gnd 3 dram_d24 dram_sdqs3 dram_dqm3 dram_d11 dram_d10 nc nc gnd dram_a8 nc nc dram_a5 gnd nc nc dram_a2 gnd nc nc dram_d5 dram_d4 dram_dqm2 dram_sdqs2 dram_d23 2 dram_sdqs3_b dram_d15 dram_d13 gnd dram_d8 dram_sdqs1_b dram_dqm1 zqpad dram_a10 dram_a15 dram_cs1 dram_sdcke1 dram_cs0 sdcke0 dram_a14 dram_a11 dram_a12 dram_dqm0 dram_sdqs0 dram_d7 gnd dram_d2 dram_d0 dram_sdqs2_b 1 gnd dram_d14 dram_d12 gnd dram_d9 dram_sdqs1 gnd dram_sdba2 dram_sdba0 gnd dram_sdclk_0 dram_sdclk_0_b dram_ras dram_cas gnd dram_sdba1 dram_sdwe gnd dram_sdqs0_b dram_d6 gnd dram_d3 dram_d1 gnd table 68. 13 x 13 mm, 0.5 mm pitch ball map (continued) a b c d e f g h j k l m n p r t u v w y aa ab ac ad
revision history i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 101 7 revision history table 70 provides a history for revision 4 of this data sheet. table 70. i.mx 6sololite data sheet document revision history rev. number date substantive change(s) 5 9/2017 ? figure 1, "part number nomenclaturei.mx 6sololite updates to the silicon revision column to include rev. 1.4, c. ? table 1, "example orderable part numbers added c suffix part numbers and descriptions. ? section 4.8.2, ddr i/o output buffer impedance cross-reference change from jedec standards to mmdc section. ? table 42, "emmc4.4/4.41 interface timing parameters , corrected sd3 minimum from 2.6 to 1.7 ns. ? table 42, "emmc4.4/4.41 interface timing parameters , added footnote related to clock duty cycle range. ? figure 30, "hs200 mode timing diagram updated figure to remove extraneous id callouts. ( revision history table continued on next page )
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 102 nxp semiconductors revision history 4 11/2016 ? changed throughout: C changed terminology from floating to not connected. C removed references to ddr3 ? section 1, introduction , i.mx 6sololite processor features removed low voltage ddr3 from second paragraph. ? table 1, "example orderable part numbers : added new footnote to speed grade heading. C removed paragraph about selecting the right data sheet. C removed silicon revision 1 part numbers ending in aa. ? figure 1, "part number nomenclaturei.mx 6sololite : added to silicon revision block rev 1.3 and associated footnote. ? section 1.2, features , added new bullet under expansion cards, 4-bit or 8-bit ? table 2, "i.mx 6sololite modules list : uart1C5, uart interface row: C changed bullet about programmable baud rate to up to 5 mbps. C added new bullet at top: conforms to the sd host controller C added version 4.5 to mmcs specifications listed in second bullet fully compliant with mmc C added new bullet 4-bit or 8-bit transfer mode ? table 3, "special signal considerations , content changes in the following rows: C xtalosc_clk1_p/ xtalosc_clk1_n: changed floating to unconnected. C nc: changed floating to remain unconnected. C src_por_b: removed second sentence may be used C rtc_xtali/ rtc_xtalo: changed floating to unconnected. C rtc_xtali/ rtc_xtalo: changed keep rtc_xtalo floating to leave rtc_xtalo unconnected. C test_mode: changed float this signal to leave this signal unconnected. C xtali/ xtalo: changed floated to remains unconnected. C separated paragraphs with bullets. ? table 5, "recommended connections for unused analog interfaces : changed float to leave unconnected in both lines. ? section 4.1.1, absolute maximum ratings : added new caution text. ? table 7, "absolute maximum ratings ,: C updated the maximum voltage specific ations to an increased of 100 mv. C nvcc_dram maximum value changed to 1.975 v. C added footnote regarding nvcc_dram maximum voltage allowance. C added row to vin/vout supply voltage, separating ddr pins and non-ddr pins and included footnote regarding maximum voltage allowance. ? section 4.1.2.1, bga case 2240 package thermal resistance added note per jedec jesd51-2. ? table 9, "operating ranges , changed within rows: C backup battery supply range, minimum reduced (improved) from 2.8 to 2.7. C backup battery supply range, maximum increased (improved) from 3.3 to 3.6 C removed from the gpio supplies row; nvcc_1p2v row for ddr3l ? section 4.1.5, maximu m supply currents , paragraph 3: changed an4715 to an4580. ? section 4.2.1, power-up sequence , removed reference to external src_por_b: C bullet 3: removed if the external and final sentence in the absence of C removed bullet 4. C added third note: for customers starting new designs continued on next page table 70. i.mx 6sololite data sheet document revision history (continued) rev. number date substantive change(s)
revision history i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 103 4 continued 11/2016 ? section 4.2.2, power-down sequence , replaced contents of section with sentence: there are no special requirements on the power-down sequence other than . ? section 4.5.2, osc32k : removed text regarding coin cell from third paragraph and removed second note about third party coin cell manufacturer. ? section 4.6, i/o dc parameters : removed second bullet regarding single voltage gpio cell set. ? section 4.6.1, xtali and rtc_xtali (clock inputs) dc parameters added note after table. table 20, "xtali and rtc_xtali dc parameters : C added parameter rows: input capacitance; xtali input leakage; and dc input current. C added new footnote, thi s voltage specification ? section 4.6.3, single voltage general purpose i/o (gpio) dc parameters? removed section. ? section 4.8, output buffer impedance parameters : removed second bullet single voltage general purpose i/o cell set . ? table 28, "dvgpio output buffer average impedance (ovdd 1.8 v) : changed all typical values. ? table 29, "dvgpio output buffer average impedance (ovdd 3.3 v) : changed all typical values. ? section 4.8.2, single voltage gpio output buffer impedance : removed section. ? table 34, "eim bus timing parameters , updates throughout table to include min/max values. ? table 35, "eim asynchronous timing parameters table relative chip select , updates throughout table to include min/max values. ? section 4.9.4, multi-mode ddr controller (mmdc) , created this new section. ? removed: section 4.9.5, ddr sdram s pecific parameters (ddr3 and lpddr2), section 4.9.5.1, ddr3 parameters, and section 4.9.5.2, lpddr2 parameters. ? table 37, "csi gated clock mode timing parameters , C parameter p5 reduced (impro ved) from 10ns to 7.5 ns. C parameter p6 reduced (impro ved) from 10ns to 7.5 ns. C parameter p7 corrected to 66 mhz (no functional change). ? table 38, "csi ungated clock mode timing parameters , C parameter p4 reduced (impro ved) from 10ns to 7.5 ns. C parameter p5 reduced (impro ved) from 10ns to 7.5 ns. C parameter p6 corrected to 66 mhz (no functional change). ? section 4.10.3.1, ecspi master mode timing , added new note under figure 25 . ? section 4.10.3.2, ec spi slave mode timing , added new note under figure 26 . ? section 4.10.4.3, sdr50/sdr104 ac timing parameters , figure 29 updated to correct sd5. ? table 43, "sdr50/sdr104 interface timing parameters , C sd2, changed minimum value to 0.46, and changed maximum value to 0.54. C sd3, changed minimum value to 0.46, and changed maximum value to 0.54. C sd2 (parameter clock high time), parameter name corrected to sd3. C sd5, changed maximum value to 0.74. ? section 4.10.5, hs200 mode timing parameters , added this new section. ? section 4.10.14, usb phy parameters , added new text to second paragraph usb host with the amendments below ? table 63, "interfaces allocation during boot usdhc-1Cusdhc-4 row, replaced existing text with refer to the table sd/mmc ? table 65, "13 x 13 mm supplies contact assignment , C gpanaio: changed remark from analog pad to analog output for nxp use C zqpad: changed remark to connect zqpad to ? table 66, "13 x 13 mm functional contact assignments , dram_sdclk_0, corrected input to output and value to 0. ? section 6.2.2, 13 x 13 mm ground, power, sense, not connected, and reference contact assignments , added new text for most of the signals after ta bl e 6 6 . ? table 68, "13 x 13 mm, 0.5 mm pitch ball map , ball ad6 name corrected to dram_d18. table 70. i.mx 6sololite data sheet document revision history (continued) rev. number date substantive change(s)
i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 104 nxp semiconductors revision history rev. 3 02/2014 ? section 1.2, feature description for: - camera sensors: added to parallel camera port and up to 66 mhz peak. - miscellaneous ips and interfaces; changed from: three i2s/ssi/ac97 supported, to ssi block is capable of supporting audio sample frequencies up to 192 khz stereo inputs and outputs with i2s mode. ? ta b l e 2 , modules list: uart1C5, brief description; changed bullet about programmable baud rate to up to 5 mhz. ? ta b l e 2 , modules list: usdhc1C4, brief description; changed bullet about fully compliant with sd command/response to include and sdxc cards up to 2tb. ? ta b l e 9 , operating range for gpio supplies: added nvcc_1p2v min/typ/max values for lpddr2, ddr3l, ddr3. ? section 4.1.4, external clock sources; added note, the internal oscillator may run high ? ta b l e 1 1 , maximum supply currents: added row; nvcc_lvds2p5. ? section 4.2.1, power-up sequence: reworded third bulleted item regarding por control. ? section 4.2.1, power-up sequence: removed note. ? section 4.5.1, osc24k, first paragraph corrected powered from signal from nvcc_1p2 to nvcc_1p2v. ? section 4.5.2, osc32k, changed second paragraph and added caution. ? ta b l e 3 1 reset timing parameters, changed unit from xtali cycle to xtalosc_rtc_xtali cycle. ? section 4.5.2, external interface module; enhanced wording to first paragraph to describe operating frequency for data transfers, and to explain register settings are valid for entire range of frequencies. ? ta b l e 3 4 , eim bus timing parameters; reworded footnotes for clarity. rev. 3.0 02/2014 ? table 45, ddr3 write cycle; change d footnote 3, outputs from ddr_vref to dram_vref. ? figure 25, lpddr2 command and address timing diagram; changed signal name from dram_cas_b to dram_addrxx. ? table 47, lpddr2 timing parameters; cha nged footnote 2, outputs from ddr_vref to dram_vref. ? table 48, lpddr2 write cycle; changed footno te 3, outputs from ddr_vref to dram_vref. ? table 49, lpddr2 read cycle; changed footnote 3, outputs from ddr_vref to dram_vref. ? ta b l e 6 5 , 13x13mm supplies contact assignment; c hanged supply rail name ddr_vref to dram_vref. ? ta b l e 6 5 , 13x13mm supplies contact assignment; changed zqpad ball position from ae17 to h2. ? ta b l e 6 8 , 13x13mm functional contact assignment; changed the following signals to include active-low _b in the default function column: dram_cas_b; dram_cs0_b; dram_cs1_b; dram_ras_b; dram_reset_b. ? ta b l e 6 8 , 13x13mm functional contact assignment; changed the ball name of dram_we_b to dram_sdwe. ? ta b l e 6 8 , 13 x 13 mm, 0.5 mm pitch ball map; y19, changed from on/off to nvcc_pll. ? ta b l e 6 8 , 13 x 13 mm, 0.5 mm pitch ball map; w18, changed from test_m ode to on/off. ? ta b l e 6 8 , 13 x 13 mm, 0.5 mm pitch ball map; u15, changed from nvcc_pll to test_mode. ? ta b l e 6 8 , 13 x 13 mm, 0.5 mm pitch ball map; u11 & u10, changed from nhvcc_3v3 to nvcc33_io. rev. 2.2 8/2013 substantive changes are as follows: ? section 1.2, features , corrected value of ocram from 256kb to 128kb: the soc-level memory system consists of the following add itional components: boot rom, including hab (96 kb) internal multimedia / shared, fast access ram (ocram, 128 kb) ? removed parenthetic al statement (input slope <= 5 ns) from ta bl e 3 1 , reset timing parameters cc1: duration of por_b to be qualified as valid. the parenthetical statement was a typographical error and is not a specification requirement for this device. table 70. i.mx 6sololite data sheet document revision history (continued) rev. number date substantive change(s)
revision history i.mx 6sololite applications processors for consumer products, data sheet, rev. 5, 10/2017 nxp semiconductors 105 rev. 2.1 05/2013 substantive changes th roughout this document are as follows: ? incorporated standardized signal names. this change is extensive throughout the document. ? added section section 1.3, updated signal naming convention . ? added reference to eb792, i.mx signal name mapping. ? figures updated to align to standardized signal names. ? updated references to emmc standard to include 4.41. ? references to consumer and extended consum er temperature grades changed to commercial and extended commercial. ? figure 1 part number nomenclaturei.mx 6sololite, updates to silicon revision section. ? ta b l e 1 orderable part numbers part numbers updated and options updated accordingly. ? ta b l e 2 i.mx 6sololite modules list changed reference to global power controller to read general power controller. ? ta b l e 1 2 . stop mode current and power consumption added snvs only mode information. ? ta b l e 3 9 ecspi master mode timing parameters, updated cs5/cs6 min to half ecspix_sclk period-4/half ecspix_sclk period-2. ? ta b l e 3 9 ecspi master mode timing parameters, added to cs8 parameters slow group/fast group. ? ta b l e 4 1 sd/emmc4.3 interface timing specificat ion, changed sd8 from 5.6ns to 1.5ns. ? ta b l e 6 6 13 x 13 mm functional contact assignments, changes throughout. nvcc_gpio, nvcc_sd1, nvcc_sd2, nvcc_sd3, and nvcc_lcd entries in the power group column changed to nvcc33_io or nvcc18_io. ? ta b l e 6 6 13 x 13 mm functional contact assignments, added footnote to value to include reference information to pull-up and pull-down strengths. rev. 2.1 05/2013 ? ta b l e 6 6 : 13 x 13 mm functional contact assi gnments, for contact ecspi_mosi through ecspi2_sclk changed ball type from alt5 to gpio. ? section 1.2, features , added bulleted items regarding the soc-level memory system. ? renamed and updated section 4.3.2, regulators for analog modules . ? section 4.10.6, fec ac timing parameters , removed fec mii subsections and other references to miichanged to rmii as applicable. ? removed section, eim signal cross referenc e. signal names are now aligned between reference manual and data sheet. table 70. i.mx 6sololite data sheet document revision history (continued) rev. number date substantive change(s)
document number: IMX6SLCEC rev. 5 10/2017 how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provid ed solely to enable system and software implementers to use nxp products. there ar e no express or implied copyright licenses granted hereunder to design or fabricat e any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions. nxp, the nxp logo, nxp secure connections for a smarter world, i2c bus, freescale, the freescale logo, and the energy efficient solutions logo, are trademarks of nxp b.v. arm, the arm powered logo, and cortex-a9, and trustzone are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. mpcore and neon are trademarks of arm limited (or its subidiaries) in the eu and/or elsewhere. all rights reserved. all other product or service names are the property of their respective owners. ? 2012-2017 nxp b.v.

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